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Date:   Fri, 27 Mar 2020 14:23:13 +0100
From:   Andrew Lunn <andrew@lunn.ch>
To:     Florinel Iordache <florinel.iordache@nxp.com>
Cc:     "davem@davemloft.net" <davem@davemloft.net>,
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        "f.fainelli@gmail.com" <f.fainelli@gmail.com>,
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        "linux@armlinux.org.uk" <linux@armlinux.org.uk>,
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        "linux-doc@vger.kernel.org" <linux-doc@vger.kernel.org>,
        "robh+dt@kernel.org" <robh+dt@kernel.org>,
        "mark.rutland@arm.com" <mark.rutland@arm.com>,
        "kuba@kernel.org" <kuba@kernel.org>,
        "corbet@lwn.net" <corbet@lwn.net>,
        "shawnguo@kernel.org" <shawnguo@kernel.org>,
        Leo Li <leoyang.li@nxp.com>,
        "Madalin Bucur (OSS)" <madalin.bucur@oss.nxp.com>,
        Ioana Ciornei <ioana.ciornei@nxp.com>,
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Subject: Re: [EXT] Re: [PATCH net-next 6/9] net: phy: add backplane kr driver
 support
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On Fri, Mar 27, 2020 at 01:02:17PM +0000, Florinel Iordache wrote:
> > > +static u32 le_ioread32(void __iomem *reg) {
> > > +     return ioread32(reg);
> > > +}
> > > +
> > > +static void le_iowrite32(u32 value, void __iomem *reg) {
> > > +     iowrite32(value, reg);
> > > +}
> > > +
> > > +static u32 be_ioread32(void __iomem *reg) {
> > > +     return ioread32be(reg);
> > > +}
> > > +
> > > +static void be_iowrite32(u32 value, void __iomem *reg) {
> > > +     iowrite32be(value, reg);
> > > +}
> > 
> > This is very surprising to me. I've not got my head around the structure of this
> > code yet, but i'm surprised to see memory mapped access functions in generic
> > code.
> > 
> >        Andrew
> 
> Hi Andrew,
> 
> This is part of the framework used to automatically setup desired I/O 
> callbacks for memory access according to device specific endianness 
> which is specified in the specific device tree (DTS).
> This approach (explained below) was used to avoid the potential 
> redundant code related to memory access LE/BE which should be 
> similar for all devices. 

All devices which are using mmio. I assume the standard does not say
anything about memory mapped IO. It talks just about MDIO registers.

I would expect the generic code to just have generic accessors, which
could work for MMIO, yet more MDIO registers, i2c, spi, etc.

So add another support file which adds an MMIO implementation of these
generic access functions. Any driver which uses MMIO can pull it in.
The same should be true for the DT binding. Don't assume MMIO in the
generic binding.

> This portion of code is just preparing these four static IO routines 
> for specific endianness access LE/BE

Linux has a lot of MMIO accessors. Are you sure there is not one which
will do the right thing, making use of cpu_le32() or cpu_be32()
etc. Or are there different variants of the hardware, with some using
BE registers and some using LE registers? Note, this is all about the
endianness of the register, not the endianness of the cpu. cpu_le32()
will be a NOP when the CPU is running LE.

     Andrew