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Cc:     baolu.lu@linux.intel.com, "Liu, Yi L" <yi.l.liu@intel.com>,
        "Raj, Ashok" <ashok.raj@intel.com>,
        Christoph Hellwig <hch@infradead.org>,
        Jonathan Cameron <jic23@kernel.org>,
        Eric Auger <eric.auger@redhat.com>
Subject: Re: [PATCH V10 03/11] iommu/vt-d: Add a helper function to skip agaw
To:     "Tian, Kevin" <kevin.tian@intel.com>,
        Jacob Pan <jacob.jun.pan@linux.intel.com>,
        "iommu@lists.linux-foundation.org" <iommu@lists.linux-foundation.org>,
        LKML <linux-kernel@vger.kernel.org>,
        Joerg Roedel <joro@8bytes.org>,
        David Woodhouse <dwmw2@infradead.org>,
        Alex Williamson <alex.williamson@redhat.com>,
        Jean-Philippe Brucker <jean-philippe@linaro.com>
References: <1584746861-76386-1-git-send-email-jacob.jun.pan@linux.intel.com>
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From:   Lu Baolu <baolu.lu@linux.intel.com>
Message-ID: <d17053c3-9a40-837a-dffa-57492cded028@linux.intel.com>
Date:   Sun, 29 Mar 2020 15:20:55 +0800
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On 2020/3/27 19:53, Tian, Kevin wrote:
>> From: Jacob Pan <jacob.jun.pan@linux.intel.com>
>> Sent: Saturday, March 21, 2020 7:28 AM
>>
>> Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
> 
> could you elaborate in which scenario this helper function is required?

I added below commit message:

     An Intel iommu domain uses 5-level page table by default. If the
     iommu that the domain tries to attach supports less page levels,
     the top level page tables should be skipped. Add a helper to do
     this so that it could be used in other places.

Best regards,
baolu

>   
>> ---
>>   drivers/iommu/intel-pasid.c | 22 ++++++++++++++++++++++
>>   1 file changed, 22 insertions(+)
>>
>> diff --git a/drivers/iommu/intel-pasid.c b/drivers/iommu/intel-pasid.c
>> index 22b30f10b396..191508c7c03e 100644
>> --- a/drivers/iommu/intel-pasid.c
>> +++ b/drivers/iommu/intel-pasid.c
>> @@ -500,6 +500,28 @@ int intel_pasid_setup_first_level(struct intel_iommu
>> *iommu,
>>   }
>>
>>   /*
>> + * Skip top levels of page tables for iommu which has less agaw
>> + * than default. Unnecessary for PT mode.
>> + */
>> +static inline int iommu_skip_agaw(struct dmar_domain *domain,
>> +				  struct intel_iommu *iommu,
>> +				  struct dma_pte **pgd)
>> +{
>> +	int agaw;
>> +
>> +	for (agaw = domain->agaw; agaw > iommu->agaw; agaw--) {
>> +		*pgd = phys_to_virt(dma_pte_addr(*pgd));
>> +		if (!dma_pte_present(*pgd)) {
>> +			return -EINVAL;
>> +		}
>> +	}
>> +	pr_debug_ratelimited("%s: pgd: %llx, agaw %d d_agaw %d\n",
>> __func__, (u64)*pgd,
>> +		iommu->agaw, domain->agaw);
>> +
>> +	return agaw;
>> +}
>> +
>> +/*
>>    * Set up the scalable mode pasid entry for second only translation type.
>>    */
>>   int intel_pasid_setup_second_level(struct intel_iommu *iommu,
>> --
>> 2.7.4
>