Received: by 2002:a25:6193:0:0:0:0:0 with SMTP id v141csp2332323ybb; Mon, 30 Mar 2020 04:17:39 -0700 (PDT) X-Google-Smtp-Source: ADFU+vt2V+KfLpLqwhaxW0NqNecaw+/ZbarupgCkckf2t3PqOXR8xMs4SSYb816v0DbHPyOG2nou X-Received: by 2002:a05:6830:144e:: with SMTP id w14mr9070252otp.75.1585567059252; Mon, 30 Mar 2020 04:17:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1585567059; cv=none; d=google.com; s=arc-20160816; b=oC3C3sjdACG0LfxKGhQIC2r4cZ1Yj3QP2u+G6CyZnd9g4ck2WFicyWzkxtoKlE6Fzd PdwlPcaxhrh/g0dT22RBX/b3GggrC6FBfQkRrBMerhU4Twr/YhuvlpfJseSTGPSkfpXK FvwYTT6Beu2TS2ReQJmzOXixZC5ubRbnwAig5D3+9oh/dH8fctqS0ntQgVdohl1Ksr46 vRQczm/+PuhiuoA+3ENwPvl2ZDnZCmtREiT0kBPCnfGsgLcd4VUXGQmeqTmc8W7j5cF7 rREXw1kpuAuhFwmFuLgCCdDNn6bQ4c+ar1M6SBVTQCaYq2wSTJluxE6/sKuQnF3z8o4s 53Pw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from; bh=RR4vJ9JrFqJXNe7jivas8PYz0eeIRmuqOYTugcstaRM=; b=ijBCaxT6BFizh1k1PICCmGSpaw7nnrCHBLqgvhNKqdUdu1TAQVFNxLyGyYHEAmdjK5 cf4pWX6RlDH1rJs+NRjQk+DRkZCbm3sCKJenZ/jKSR3vo00TTO0520OJIml8KRu/cDvs cafVeSJayvD/lAwmhCZJ5V/YKgqc8kunvu+epXuK3sb0lPslmJnpN8xUmGdOdtAq5g5K 6vDT4vH8+7GjYtNUtUYbVfhBdVqiW108eqmwTrmDrx3iWyArk0MVWTBTrTHUYnrOI2PC kAt+J5IxOqjfscrpLB9zQ/5WBbW6V8aiVy4yfzgedtKlZKOAGuIz1thnfceRw+JTEJXW 25Ew== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w12si6056414otq.75.2020.03.30.04.17.25; Mon, 30 Mar 2020 04:17:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729624AbgC3LRI (ORCPT + 99 others); Mon, 30 Mar 2020 07:17:08 -0400 Received: from inva020.nxp.com ([92.121.34.13]:59342 "EHLO inva020.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729267AbgC3LRI (ORCPT ); Mon, 30 Mar 2020 07:17:08 -0400 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 3E0FA1A04A7; Mon, 30 Mar 2020 13:17:06 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 218081A04A1; Mon, 30 Mar 2020 13:17:01 +0200 (CEST) Received: from lsv03124.swis.in-blr01.nxp.com (lsv03124.swis.in-blr01.nxp.com [92.120.146.121]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 44C43402AA; Mon, 30 Mar 2020 19:16:55 +0800 (SGT) From: Kuldeep Singh To: Shawn Guo , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Li Yang , Rob Herring , Mark Rutland , Kuldeep Singh , Ashish Kumar Subject: [PATCH] arm64: dts: ls1012a: Add QSPI node properties Date: Mon, 30 Mar 2020 16:46:30 +0530 Message-Id: <1585566991-24049-1-git-send-email-kuldeep.singh@nxp.com> X-Mailer: git-send-email 2.7.4 X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for QSPI on NXP layerscape LS1012A-RDB, LS1012A-QDS, LS1012A-FRDM and LS1012A-FRWY boards. LS1012A-RDB has 2 Spansion "s25fs512s" flashes of size 64M each and only one can be accessed at a time. LS1012A-QDS/FRDM has 1 spansion "s25fs512s" flash of size 64M. LS1012A-FRWY has one winbond "w25q16dw" flash of size 2M. Use generic compatibles as "jedec,spi-nor" for automatic detection of flash. Configure RX and TX buswidth values as 2 as only two I/O lines are available for data transfer. Add ls1012a(si) node alongwith flash nodes. Signed-off-by: Ashish Kumar Signed-off-by: Kuldeep Singh --- arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts | 15 +++++++++++++++ arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts | 15 +++++++++++++++ arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts | 15 +++++++++++++++ arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts | 15 +++++++++++++++ arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 13 +++++++++++++ 5 files changed, 73 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts index f90c040..6770266 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts @@ -74,6 +74,21 @@ }; }; +&qspi { + status = "okay"; + + s25fs512s0: flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + m25p,fast-read; + reg = <0>; + spi-rx-bus-width = <2>; + spi-tx-bus-width = <2>; + }; +}; + &sai2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts index 8749634..6290e2f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts @@ -23,3 +23,18 @@ &i2c0 { status = "okay"; }; + +&qspi { + status = "okay"; + + w25q16dw0: flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + m25p,fast-read; + spi-max-frequency = <50000000>; + reg = <0>; + spi-rx-bus-width = <2>; + spi-tx-bus-width = <2>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts index 2fb1cb1..449475a 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts @@ -128,6 +128,21 @@ }; }; +&qspi { + status = "okay"; + + s25fs512s0: flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + m25p,fast-read; + reg = <0>; + spi-rx-bus-width = <2>; + spi-tx-bus-width = <2>; + }; +}; + &sai2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts index 5edb1e1..d45c176 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts @@ -35,6 +35,21 @@ status = "okay"; }; +&qspi { + status = "okay"; + + s25fs512s0: flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + m25p,fast-read; + reg = <0>; + spi-rx-bus-width = <2>; + spi-tx-bus-width = <2>; + }; +}; + &sata { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi index 3379193..006e544 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -137,6 +137,19 @@ #size-cells = <2>; ranges; + qspi: spi@1550000 { + compatible = "fsl,ls1021a-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x1550000 0x0 0x10000>, + <0x0 0x40000000 0x0 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = ; + clock-names = "qspi_en", "qspi"; + clocks = <&clockgen 4 0>, <&clockgen 4 0>; + status = "disabled"; + }; + esdhc0: esdhc@1560000 { compatible = "fsl,ls1012a-esdhc", "fsl,esdhc"; reg = <0x0 0x1560000 0x0 0x10000>; -- 2.7.4