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From:   Dan Williams <dan.j.williams@intel.com>
Date:   Wed, 1 Apr 2020 01:48:32 -0700
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Subject: Re: [PATCH v4 03/25] powerpc/powernv: Map & release OpenCAPI LPC memory
To:     "Alastair D'Silva" <alastair@d-silva.org>
Cc:     "Aneesh Kumar K . V" <aneesh.kumar@linux.ibm.com>,
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        Andrew Donnellan <ajd@linux.ibm.com>,
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On Sun, Mar 29, 2020 at 10:23 PM Alastair D'Silva <alastair@d-silva.org> wrote:
>
> This patch adds OPAL calls to powernv so that the OpenCAPI
> driver can map & release LPC (Lowest Point of Coherency)  memory.
>
> Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com>
> ---
>  arch/powerpc/include/asm/pnv-ocxl.h   |  2 ++
>  arch/powerpc/platforms/powernv/ocxl.c | 43 +++++++++++++++++++++++++++
>  2 files changed, 45 insertions(+)
>
> diff --git a/arch/powerpc/include/asm/pnv-ocxl.h b/arch/powerpc/include/asm/pnv-ocxl.h
> index 7de82647e761..560a19bb71b7 100644
> --- a/arch/powerpc/include/asm/pnv-ocxl.h
> +++ b/arch/powerpc/include/asm/pnv-ocxl.h
> @@ -32,5 +32,7 @@ extern int pnv_ocxl_spa_remove_pe_from_cache(void *platform_data, int pe_handle)
>
>  extern int pnv_ocxl_alloc_xive_irq(u32 *irq, u64 *trigger_addr);
>  extern void pnv_ocxl_free_xive_irq(u32 irq);
> +u64 pnv_ocxl_platform_lpc_setup(struct pci_dev *pdev, u64 size);
> +void pnv_ocxl_platform_lpc_release(struct pci_dev *pdev);
>
>  #endif /* _ASM_PNV_OCXL_H */
> diff --git a/arch/powerpc/platforms/powernv/ocxl.c b/arch/powerpc/platforms/powernv/ocxl.c
> index 8c65aacda9c8..f13119a7c026 100644
> --- a/arch/powerpc/platforms/powernv/ocxl.c
> +++ b/arch/powerpc/platforms/powernv/ocxl.c
> @@ -475,6 +475,49 @@ void pnv_ocxl_spa_release(void *platform_data)
>  }
>  EXPORT_SYMBOL_GPL(pnv_ocxl_spa_release);
>
> +u64 pnv_ocxl_platform_lpc_setup(struct pci_dev *pdev, u64 size)
> +{
> +       struct pci_controller *hose = pci_bus_to_host(pdev->bus);
> +       struct pnv_phb *phb = hose->private_data;

Is calling the local variable 'hose' instead of 'host' on purpose?

> +       u32 bdfn = pci_dev_id(pdev);
> +       __be64 base_addr_be64;
> +       u64 base_addr;
> +       int rc;
> +
> +       rc = opal_npu_mem_alloc(phb->opal_id, bdfn, size, &base_addr_be64);
> +       if (rc) {
> +               dev_warn(&pdev->dev,
> +                        "OPAL could not allocate LPC memory, rc=%d\n", rc);
> +               return 0;
> +       }
> +
> +       base_addr = be64_to_cpu(base_addr_be64);
> +
> +#ifdef CONFIG_MEMORY_HOTPLUG_SPARSE

With the proposed cleanup in patch2 the ifdef can be elided here.

> +       rc = check_hotplug_memory_addressable(base_addr >> PAGE_SHIFT,
> +                                             size >> PAGE_SHIFT);
> +       if (rc)
> +               return 0;

Is this an error worth logging if someone is wondering why their
device is not showing up?


> +#endif
> +
> +       return base_addr;
> +}
> +EXPORT_SYMBOL_GPL(pnv_ocxl_platform_lpc_setup);
> +
> +void pnv_ocxl_platform_lpc_release(struct pci_dev *pdev)
> +{
> +       struct pci_controller *hose = pci_bus_to_host(pdev->bus);
> +       struct pnv_phb *phb = hose->private_data;
> +       u32 bdfn = pci_dev_id(pdev);
> +       int rc;
> +
> +       rc = opal_npu_mem_release(phb->opal_id, bdfn);
> +       if (rc)
> +               dev_warn(&pdev->dev,
> +                        "OPAL reported rc=%d when releasing LPC memory\n", rc);
> +}
> +EXPORT_SYMBOL_GPL(pnv_ocxl_platform_lpc_release);
> +
>  int pnv_ocxl_spa_remove_pe_from_cache(void *platform_data, int pe_handle)
>  {
>         struct spa_data *data = (struct spa_data *) platform_data;
> --
> 2.24.1
>