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[209.132.180.67]) by mx.google.com with ESMTP id j11si553407ota.85.2020.04.01.01.52.57; Wed, 01 Apr 2020 01:53:09 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@st.com header.s=STMicroelectronics header.b=Bz5kj7th; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=st.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731850AbgDAIwW (ORCPT + 99 others); Wed, 1 Apr 2020 04:52:22 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:17490 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727627AbgDAIwW (ORCPT ); Wed, 1 Apr 2020 04:52:22 -0400 Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 0318mpWe009234; Wed, 1 Apr 2020 10:52:08 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=subject : to : cc : references : from : message-id : date : mime-version : in-reply-to : content-type : content-transfer-encoding; s=STMicroelectronics; bh=vu4qQWypR0pvt6vGhb+hu2zbxKSw9Xfk1eNnrYVVjv0=; b=Bz5kj7thRXHC1yRZ1OgULStYl0DaHIznaEan7Ase11XZ1sc9x8sL7teQc1JFPLYC+Im5 ifwjAyXEU4WWfr+xelyILT9/TCw9fs3cPj4b0qa5KGOxye+GGeXJR2ULwEPb4X47SX9t MzH+MNq+jLX4/u0PMZlqgmMm0yb05L+/kiP/6hsNpPkusGJE8HITAXqbm9fZA8rkMC0T WJVyPRhnF1NTRjmxdz2YmS8UYxJjaSgfyGQBuH1Q1dPA/EUG4Y+YQBpQT7Qyoj1YaE7K OH/5wYFFf9UgZdHli+ae7HRf7epZfstEz92URSCMMXHK8pHxRS0xREIzT9ISQbWMlG7K mQ== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 302y53x4nc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 01 Apr 2020 10:52:08 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 2C7B510002A; Wed, 1 Apr 2020 10:52:08 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag5node3.st.com [10.75.127.15]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 1D83021D6CB; Wed, 1 Apr 2020 10:52:08 +0200 (CEST) Received: from [10.211.14.17] (10.75.127.46) by SFHDAG5NODE3.st.com (10.75.127.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 1 Apr 2020 10:52:06 +0200 Subject: Re: [PATCH v6 3/6] mfd: stm32: Add defines to be used for clkevent purpose To: Benjamin Gaignard , , , , , , , CC: , , , References: <20200401083909.18886-1-benjamin.gaignard@st.com> <20200401083909.18886-4-benjamin.gaignard@st.com> From: Fabrice Gasnier Message-ID: Date: Wed, 1 Apr 2020 10:52:06 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <20200401083909.18886-4-benjamin.gaignard@st.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.75.127.46] X-ClientProxiedBy: SFHDAG4NODE2.st.com (10.75.127.11) To SFHDAG5NODE3.st.com (10.75.127.15) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138,18.0.676 definitions=2020-03-31_07:2020-03-31,2020-03-31 signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 4/1/20 10:39 AM, Benjamin Gaignard wrote: > Add defines to be able to enable/clear irq and configure one shot mode. > > Signed-off-by: Benjamin Gaignard > Acked-by: Lee Jones > --- > include/linux/mfd/stm32-lptimer.h | 5 +++++ > 1 file changed, 5 insertions(+) Hi Benjamin, Acked-by: Fabrice Gasnier Thanks, Fabrice > > diff --git a/include/linux/mfd/stm32-lptimer.h b/include/linux/mfd/stm32-lptimer.h > index 605f62264825..90b20550c1c8 100644 > --- a/include/linux/mfd/stm32-lptimer.h > +++ b/include/linux/mfd/stm32-lptimer.h > @@ -27,10 +27,15 @@ > #define STM32_LPTIM_CMPOK BIT(3) > > /* STM32_LPTIM_ICR - bit fields */ > +#define STM32_LPTIM_ARRMCF BIT(1) > #define STM32_LPTIM_CMPOKCF_ARROKCF GENMASK(4, 3) > > +/* STM32_LPTIM_IER - bit flieds */ > +#define STM32_LPTIM_ARRMIE BIT(1) > + > /* STM32_LPTIM_CR - bit fields */ > #define STM32_LPTIM_CNTSTRT BIT(2) > +#define STM32_LPTIM_SNGSTRT BIT(1) > #define STM32_LPTIM_ENABLE BIT(0) > > /* STM32_LPTIM_CFGR - bit fields */ >