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From:   Nadav Amit <namit@vmware.com>
To:     Wanpeng Li <kernellwp@gmail.com>
CC:     Paolo Bonzini <pbonzini@redhat.com>,
        LKML <linux-kernel@vger.kernel.org>, kvm <kvm@vger.kernel.org>,
        Sean Christopherson <sean.j.christopherson@intel.com>,
        Vitaly Kuznetsov <vkuznets@redhat.com>,
        Wanpeng Li <wanpengli@tencent.com>,
        Jim Mattson <jmattson@google.com>,
        Joerg Roedel <joro@8bytes.org>
Subject: Re: [PATCH v2 2/2] KVM: LAPIC: Don't need to clear IPI delivery
 status in x2apic mode
Thread-Topic: [PATCH v2 2/2] KVM: LAPIC: Don't need to clear IPI delivery
 status in x2apic mode
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Date:   Wed, 1 Apr 2020 17:40:03 +0000
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> On Mar 31, 2020, at 11:46 PM, Wanpeng Li <kernellwp@gmail.com> wrote:
>=20
> Cc more people,
> On Wed, 1 Apr 2020 at 08:35, Paolo Bonzini <pbonzini@redhat.com> wrote:
>> On 01/04/20 02:19, Wanpeng Li wrote:
>>> -             /* No delay here, so we always clear the pending bit */
>>> -             val &=3D ~(1 << 12);
>>> +             /* Immediately clear Delivery Status in xAPIC mode */
>>> +             if (!apic_x2apic_mode(apic))
>>> +                     val &=3D ~(1 << 12);
>>=20
>> This adds a conditional, and the old behavior was valid according to the
>> SDM: "software should not assume the value returned by reading the ICR
>> is the last written value".
>=20
> Nadav, Sean, what do you think?

I do not know. But if you write a KVM unit-test, I can run it on bare-metal
and give you feedback about how it behaves.