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Date:   Wed, 1 Apr 2020 16:01:00 -0700
From:   Sean Christopherson <sean.j.christopherson@intel.com>
To:     Nadav Amit <namit@vmware.com>
Cc:     Wanpeng Li <kernellwp@gmail.com>,
        Paolo Bonzini <pbonzini@redhat.com>,
        LKML <linux-kernel@vger.kernel.org>, kvm <kvm@vger.kernel.org>,
        Vitaly Kuznetsov <vkuznets@redhat.com>,
        Wanpeng Li <wanpengli@tencent.com>,
        Jim Mattson <jmattson@google.com>,
        Joerg Roedel <joro@8bytes.org>
Subject: Re: [PATCH v2 2/2] KVM: LAPIC: Don't need to clear IPI delivery
 status in x2apic mode
Message-ID: <20200401230100.GE9603@linux.intel.com>
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On Wed, Apr 01, 2020 at 05:40:03PM +0000, Nadav Amit wrote:
> > On Mar 31, 2020, at 11:46 PM, Wanpeng Li <kernellwp@gmail.com> wrote:
> > 
> > Cc more people,
> > On Wed, 1 Apr 2020 at 08:35, Paolo Bonzini <pbonzini@redhat.com> wrote:
> >> On 01/04/20 02:19, Wanpeng Li wrote:
> >>> -             /* No delay here, so we always clear the pending bit */
> >>> -             val &= ~(1 << 12);
> >>> +             /* Immediately clear Delivery Status in xAPIC mode */
> >>> +             if (!apic_x2apic_mode(apic))
> >>> +                     val &= ~(1 << 12);
> >> 
> >> This adds a conditional, and the old behavior was valid according to the
> >> SDM: "software should not assume the value returned by reading the ICR
> >> is the last written value".
> > 
> > Nadav, Sean, what do you think?
> 
> I do not know. But if you write a KVM unit-test, I can run it on bare-metal
> and give you feedback about how it behaves.

I agree with Paolo, clearing the bit doesn't violate the SDM.  The
conditional is just as costly as the AND, if not more so, even for x2APIC.

I would play it safe and clear the bit even in the x2APIC only path to
avoid tripping up guest kernels that loop on the delivery status even when
using x2APIC.