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Miller" , Maxime Coquelin CC: "netdev@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "Giuseppe Cavallaro" , Andrew Lunn , Alexandre Torgue , "Ong, Boon Leong" Subject: RE: [RFC,net-next,v1, 1/1] net: stmmac: Enable SERDES power up/down sequence Thread-Topic: [RFC,net-next,v1, 1/1] net: stmmac: Enable SERDES power up/down sequence Thread-Index: AQHWAE03JZEV2gP9CkiKXaQcDq7OzahVzGeAgAAJs4CAAAleQIAAdfeAgA4MGYCAATPU0A== Date: Thu, 2 Apr 2020 08:47:19 +0000 Message-ID: References: <20200322132342.2687-1-weifeng.voon@intel.com> <20200322132342.2687-2-weifeng.voon@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=joabreu@synopsys.com; x-originating-ip: [82.155.99.6] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 1c101dfb-54be-4a6f-c844-08d7d6e2740e x-ms-traffictypediagnostic: BN8PR12MB3091: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:9508; x-forefront-prvs: 0361212EA8 x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:BN8PR12MB3266.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFTY:;SFS:(10019020)(396003)(39860400002)(136003)(366004)(346002)(376002)(8676002)(186003)(5660300002)(66556008)(86362001)(52536014)(71200400001)(8936002)(81166006)(4326008)(478600001)(66446008)(26005)(33656002)(9686003)(6506007)(2906002)(76116006)(66476007)(81156014)(55016002)(64756008)(316002)(66946007)(7696005)(54906003)(110136005)(142933001);DIR:OUT;SFP:1102; received-spf: None (protection.outlook.com: synopsys.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: XkpQcCnxa79t7ARjE+9m7MabWmH0v8/1RO3OdUOxMGHrhqS1SIZFGTNxU6rY4d9Ih812JNhVjnpP9QDoxjjFnZ3w/+XC0VJWhngiX3zZw+gpWU0JTP4j9HifMPxPz+k22tvuzzIMjqVyRUUmsNcyvzieeZO0Ta2IAgDvspEtH4iXcSZxqblRgafCAZbfFaFn4JEwAQCKTNMVNtOk09IL0lkUAB1o4IfqZvckETmVH6VhPSBIPQGX47rUM+6VCAueEXBrCpJ1sosnzam/a1jTxKxzWurQhjsQCUiDsayPplA7RVN0vxoeXQiGpW1HIGsIVHcdIllPkH/GCbRi9yYPEMG+wdDrzNAfTvYyrhfEEdM9ud7WHinyOZd30JyI61Brc/A/duup8IV1A2Eg0opOQlDYxoMVaxi45KibvMmUDqMniIKxCHI9AP0fO1OugHuQEyDbLKhgtTvNimGi1wvEeM99EMCmg26mAb6ujhuj3W8Ptkt0eTmfQy0WzrZZzzPt x-ms-exchange-antispam-messagedata: UlsjHtf6TVqSDduiIOX4jIFMnhjOyKT3da2M0QIrGYFun2t+c4mHslTK3mxwA7+skz1bwuHAcxsebIcoOWnZVoz8yG6huexdOGJZ8DE5NJ2sR1q34xf89WZ+8MXbcRTUUbSIo1IOs3gojT3KfPEqCQ== x-ms-exchange-transport-forked: True Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 1c101dfb-54be-4a6f-c844-08d7d6e2740e X-MS-Exchange-CrossTenant-originalarrivaltime: 02 Apr 2020 08:47:19.3024 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: c33c9f88-1eb7-4099-9700-16013fd9e8aa X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: /vYqAOI8RIoPbiUv/qqNf+lol7fIpwzMZt/8Tlwur30/k8QzPOsjk6B9/rSczfJyg8l/LXfGJbVp/O4x5DuVDA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB3091 X-OriginatorOrg: synopsys.com Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Voon, Weifeng Date: Apr/01/2020, 15:23:09 (UTC+00:00) > > > > > > This patch is to enable Intel SERDES power up/down sequence. Th= e > > > > > > SERDES converts 8/10 bits data to SGMII signal. Below is an > > > > > > example of HW configuration for SGMII mode. The SERDES is > > > > > > located in the PHY IF in the diagram below. > > > > > > > > > > > > <-----------------GBE Controller---------->|<--External PHY > > > > > > chip--> > > > > > > +----------+ +----+ +---+ +-------= - > > -- > > > + > > > > > > | EQoS | <-GMII->| DW | < ------ > |PHY| <-SGMII-> | > > External > > > | > > > > > > | MAC | |xPCS| |IF | | PHY > > > | > > > > > > +----------+ +----+ +---+ +-------= - > > -- > > > + > > > > > > ^ ^ ^ ^ > > > > > > | | | | > > > > > > +---------------------MDIO-------------------------+ > > > > > > > > > > > > PHY IF configuration and status registers are accessible throug= h > > > > > > mdio address 0x15 which is defined as intel_adhoc_addr. During > > > > > > D0, The driver will need to power up PHY IF by changing the > > > > > > power > > > state to P0. > > > > > > Likewise, for D3, the driver sets PHY IF power state to P3. > > > > > > > > > > I don't think this is the right approach. > > > > > > > > > > You could just add a new "mdio-intel-serdes" to phy/ folder just > > > > > like I did with XPCS because this is mostly related with PHY > > > > > settings rather than EQoS. > > > > I am taking this approach to put it in stmmac folder rather than ph= y > > > > folder as a generic mdio-intel-serdes as this is a specific Intel > > > > serdes architecture which would only pair with DW EQos and DW xPCS > > HW. > > > > Since this serdes will not able to pair other MAC or other non-Inte= l > > > > platform, I would like you to reconsider this approach. I am open > > > > for > > > discussion. > > > > Thanks Jose for the fast response. > > > > > > OK, then I think we should use the BSP init/exit functions that are > > > already available for platform setups (.init and .exit callback of > > > plat_stmmacenet_data struct). We just need to extend this to PCI base= d > > > setups. > > > > > > You can take a look at stmmac_platform.c and check what's done. > > > Basically: > > > - Call priv->plat->init() at probe() and resume() > > > - Call priv->plat->exit() at remove() and suspend() > > > > > I have 2 concern if using the suggested BSP init/exit function. > > 1. Serdes is configured through MDIO bus. But the mdio bus register onl= y > > happens in stmmac_dvr_probe() in stmmac_main.c. > >=20 > > 2. All tx/rx packets requires serdes to be in the correct power state. > > If the driver power-down before stopping all the dma, it will cause tx > > queue timeout as packets are not able to be transmitted out. Hence, the > > serdes cannot be power-down before calling the stmmac_dvr_remove(). The > > stmmac_dvr_remove() will unregister the mdio bus. So, the > > driver cannot powerdown the serdes after the stmmac_dvr_remove() too. >=20 > I went through the code again, I understand that your intention is to kee= p the > platform specific setup in its own file and keep the main dwmac logic cle= an. > But, I did not see any way to separate this SERDES configuration from the= =20 > stmmac_main logic cleanly.=20 > Hope to get more ideas and discussion. Thanks. Sorry for the late reply! Yes, that's exactly my intention. Maybe we can add a new set of callbacks=20 for BSP. Something like ->start(), ->stop() ? --- Thanks, Jose Miguel Abreu