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Date:   Fri, 3 Apr 2020 15:05:48 +0200
From:   Andrew Lunn <andrew@lunn.ch>
To:     Oleksij Rempel <o.rempel@pengutronix.de>
Cc:     Florian Fainelli <f.fainelli@gmail.com>,
        Heiner Kallweit <hkallweit1@gmail.com>,
        David Jander <david@protonic.nl>,
        "David S. Miller" <davem@davemloft.net>, kernel@pengutronix.de,
        linux-kernel@vger.kernel.org, netdev@vger.kernel.org,
        Philippe Schenker <philippe.schenker@toradex.com>,
        Russell King <linux@armlinux.org.uk>
Subject: Re: [PATCH v1] net: phy: micrel: kszphy_resume(): add delay after
 genphy_resume() before accessing PHY registers
Message-ID: <20200403130548.GD114745@lunn.ch>
References: <20200403075325.10205-1-o.rempel@pengutronix.de>
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On Fri, Apr 03, 2020 at 09:53:25AM +0200, Oleksij Rempel wrote:
> After the power-down bit is cleared, the chip internally triggers a
> global reset. According to the KSZ9031 documentation, we have to wait at
> least 1ms for the reset to finish.
> 
> If the chip is accessed during reset, read will return 0xffff, while
> write will be ignored. Depending on the system performance and MDIO bus
> speed, we may or may not run in to this issue.
> 
> This bug was discovered on an iMX6QP system with KSZ9031 PHY and
> attached PHY interrupt line. If IRQ was used, the link status update was
> lost. In polling mode, the link status update was always correct.
> 
> The investigation showed, that during a read-modify-write access, the
> read returned 0xffff (while the chip was still in reset) and
> corresponding write hit the chip _after_ reset and triggered (due to the
> 0xffff) another reset in an undocumented bit (register 0x1f, bit 1),
> resulting in the next write being lost due to the new reset cycle.
> 
> This patch fixes the issue by adding a 1...2 ms sleep after the
> genphy_resume().
> 
> Fixes: 836384d2501d ("net: phy: micrel: Add specific suspend")
> Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>

Hi Oleksij

Please in future set the subject to [PATCH net v1] to indicate this is
a fix.

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew