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[209.132.180.67]) by mx.google.com with ESMTP id p2si4273062otk.220.2020.04.03.08.33.31; Fri, 03 Apr 2020 08:33:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2404348AbgDCPbX (ORCPT + 99 others); Fri, 3 Apr 2020 11:31:23 -0400 Received: from mga03.intel.com ([134.134.136.65]:18868 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2404342AbgDCPbV (ORCPT ); Fri, 3 Apr 2020 11:31:21 -0400 IronPort-SDR: SWjTOvpMierBDBsS9i9rwSXmIZtL34Xor79oDA/eVVZDdRVnAtGbdQn30FCWJEj6mYXah/OS3D otGDcBF6C6Tw== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2020 08:31:20 -0700 IronPort-SDR: OMKQRF7Fa+iUbgQ+e6v2U6cpSieyKSM7XzJhJm5+LAmhFnsLxwCxnMzjTRjWC4Fu+rYiAQvKiH /Xks5XdYTiTw== X-IronPort-AV: E=Sophos;i="5.72,340,1580803200"; d="scan'208";a="329196150" Received: from rchatre-mobl.amr.corp.intel.com (HELO [10.251.28.58]) ([10.251.28.58]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2020 08:31:20 -0700 Subject: Re: [PATCH 2/2] x86/resctrl: Support CPUID enumeration of MBM counter width To: Fenghua Yu Cc: tglx@linutronix.de, bp@alien8.de, tony.luck@intel.com, kuo-lang.tseng@intel.com, mingo@redhat.com, babu.moger@amd.com, hpa@zytor.com, x86@kernel.org, linux-kernel@vger.kernel.org References: <76dc65631c373e0c1c9f3e8aaa768f022a2c989c.1585763047.git.reinette.chatre@intel.com> <20200403000527.GI188393@romley-ivt3.sc.intel.com> From: Reinette Chatre Message-ID: <83423890-c3f5-3794-8e8b-4c0ac124cd42@intel.com> Date: Fri, 3 Apr 2020 08:31:12 -0700 User-Agent: Mozilla/5.0 (Windows NT 6.3; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.6.0 MIME-Version: 1.0 In-Reply-To: <20200403000527.GI188393@romley-ivt3.sc.intel.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Fenghua, On 4/2/2020 5:05 PM, Fenghua Yu wrote: > On Wed, Apr 01, 2020 at 10:51:02AM -0700, Reinette Chatre wrote: >> The original Memory Bandwidth Monitoring (MBM) architectural >> definition defines counters of up to 62 bits in the >> IA32_QM_CTR MSR while the first-generation MBM implementation >> uses statically defined 24 bit counters. >> >> @@ -856,6 +856,8 @@ static void init_speculation_control(struct cpuinfo_x86 *c) >> >> static void init_cqm(struct cpuinfo_x86 *c) >> { >> + c->x86_cache_mbm_width_offset = -1; >> + >> if (!cpu_has(c, X86_FEATURE_CQM_LLC)) { >> c->x86_cache_max_rmid = -1; >> c->x86_cache_occ_scale = -1; >> @@ -875,6 +877,9 @@ static void init_cqm(struct cpuinfo_x86 *c) >> >> c->x86_cache_max_rmid = ecx; >> c->x86_cache_occ_scale = ebx; >> + /* EAX contents is only defined for Intel CPUs */ >> + if (c->x86_vendor == X86_VENDOR_INTEL) >> + c->x86_cache_mbm_width_offset = eax & 0xff; > > Is it reliable to read eax which is reserved on older platforms that > don't support the feature? The new ISE specification contains an architectural redefinition of EAX. > > Seems the code assumes the reserved eax is 0 on those platforms. Is it > reliable? Testing on BDW, SKX, and CLX confirmed that EAX is 0. This addition thus results in no functional change on these systems with them continuing to use the original MBM width of 24. Reinette