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Date:   Sat, 4 Apr 2020 10:53:09 +0200
From:   Jorge Amoros-Argos <joramar76@gmail.com>
To:     linux-kernel@vger.kernel.org
Cc:     hauke@hauke-m.de, john@phrozen.org,
        martin.blumenstingl@googlemail.com
Subject: clk: Lantiq/Intel: XWAY CGU support
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Dear community,

This is addresed to the Lantiq/Intel developers for the SoC's VRX200 and
XWAY in general.

I'm trying to port the current sources to the common clock framework for
Openwrt.

For this purpose, I'd need to have a good knowledge of both clock
providers and consumers in order to update the device tree and also the
drivers. This means hardware (how devices are connected) and software
(what registers do what?)

There's no such low level detail after all my investigations, which are
shown here:

     https://github.com/Mandrake-Lee/Lantiq_XWAY_CGU

For instance, the full structure of PLL2 register remains a mistery and
also its output; OCP selector, is a kind of divider?; PCIe generator is
located where? PMU, is just a gate controller or a provider itself?

I'd really appreciate if you could share some details in order to start
the job.

Please keep me CC'd of this thread.

Thank you very much in advance,

Jorge Amor=F3s-Argos=20