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 <20200331082725.81048-5-jitao.shi@mediatek.com> <CAAOTY_8vpzfKeyxVxXOVC7mDpw+QGGOX+8fJaQg5WduvndEmoA@mail.gmail.com>
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From:   Chun-Kuang Hu <chunkuang.hu@kernel.org>
Date:   Mon, 6 Apr 2020 00:27:24 +0800
Message-ID: <CAAOTY_83pE=+WFJe3Jb8uk-8ToS_j4XN=LDLs+e_7DoYzrjdUA@mail.gmail.com>
Subject: Re: [PATCH v4 4/4] drm/mediatek: config mipitx impedance with
 calibration data
To:     Jitao Shi <jitao.shi@mediatek.com>
Cc:     Chun-Kuang Hu <chunkuang.hu@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Mark Rutland <mark.rutland@arm.com>,
        Matthias Brugger <matthias.bgg@gmail.com>,
        Daniel Vetter <daniel@ffwll.ch>,
        David Airlie <airlied@linux.ie>,
        DRI Development <dri-devel@lists.freedesktop.org>,
        linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
        srv_heupstream@mediatek.com, huijuan.xie@mediatek.com,
        stonea168@163.com, cawa.cheng@mediatek.com,
        linux-mediatek@lists.infradead.org, yingjoe.chen@mediatek.com,
        eddie.huang@mediatek.com, linux-arm-kernel@lists.infradead.org
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Hi, Jitao:

Jitao Shi <jitao.shi@mediatek.com> =E6=96=BC 2020=E5=B9=B44=E6=9C=885=E6=97=
=A5 =E9=80=B1=E6=97=A5 =E4=B8=8B=E5=8D=889:39=E5=AF=AB=E9=81=93=EF=BC=9A
>
>
> On Sat, 2020-04-04 at 22:26 +0800, Chun-Kuang Hu wrote:
> > Hi, Jitao:
> >
> > Jitao Shi <jitao.shi@mediatek.com> =E6=96=BC 2020=E5=B9=B43=E6=9C=8831=
=E6=97=A5 =E9=80=B1=E4=BA=8C =E4=B8=8B=E5=8D=884:28=E5=AF=AB=E9=81=93=EF=BC=
=9A
> > >
> > > Read calibration data from nvmem, and config mipitx impedance with
> > > calibration data to make sure their impedance are 100ohm.
> > >
> > > Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> > > ---
> > >  drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 57 +++++++++++++++++=
++
> > >  1 file changed, 57 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c b/drivers/=
gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
> > > index e4cc967750cb..0f87cd3d1d7d 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
> > > +++ b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
> > > @@ -5,6 +5,8 @@
> > >   */
> > >
> > >  #include "mtk_mipi_tx.h"
> > > +#include <linux/nvmem-consumer.h>
> > > +#include <linux/slab.h>
> > >
> > >  #define MIPITX_LANE_CON                0x000c
> > >  #define RG_DSI_CPHY_T1DRV_EN           BIT(0)
> > > @@ -28,6 +30,7 @@
> > >  #define MIPITX_PLL_CON4                0x003c
> > >  #define RG_DSI_PLL_IBIAS               (3 << 10)
> > >
> > > +#define MIPITX_D2P_RTCODE      0x0100
> > >  #define MIPITX_D2_SW_CTL_EN    0x0144
> > >  #define MIPITX_D0_SW_CTL_EN    0x0244
> > >  #define MIPITX_CK_CKMODE_EN    0x0328
> > > @@ -108,6 +111,58 @@ static const struct clk_ops mtk_mipi_tx_pll_ops =
=3D {
> > >         .recalc_rate =3D mtk_mipi_tx_pll_recalc_rate,
> > >  };
> > >
> > > +static void mtk_mipi_tx_config_calibration_data(struct mtk_mipi_tx *=
mipi_tx)
> > > +{
> > > +       u32 *buf;
> > > +       u32 rt_code[5];
> > > +       int i, j;
> > > +       struct nvmem_cell *cell;
> > > +       struct device *dev =3D mipi_tx->dev;
> > > +       size_t len;
> > > +
> > > +       cell =3D nvmem_cell_get(dev, "calibration-data");
> > > +       if (IS_ERR(cell)) {
> > > +               dev_info(dev, "nvmem_cell_get fail\n");
> > > +               return;
> > > +       }
> > > +
> > > +       buf =3D (u32 *)nvmem_cell_read(cell, &len);
> > > +
> > > +       nvmem_cell_put(cell);
> > > +
> > > +       if (IS_ERR(buf)) {
> > > +               dev_info(dev, "can't get data\n");
> > > +               return;
> > > +       }
> > > +
> > > +       if (len < 3 * sizeof(u32)) {
> > > +               dev_info(dev, "invalid calibration data\n");
> > > +               kfree(buf);
> > > +               return;
> > > +       }
> > > +
> > > +       rt_code[0] =3D ((buf[0] >> 6 & 0x1f) << 5) | (buf[0] >> 11 & =
0x1f);
> > > +       rt_code[1] =3D ((buf[1] >> 27 & 0x1f) << 5) | (buf[0] >> 1 & =
0x1f);
> > > +       rt_code[2] =3D ((buf[1] >> 17 & 0x1f) << 5) | (buf[1] >> 22 &=
 0x1f);
> > > +       rt_code[3] =3D ((buf[1] >> 7 & 0x1f) << 5) | (buf[1] >> 12 & =
0x1f);
> > > +       rt_code[4] =3D ((buf[2] >> 27 & 0x1f) << 5) | (buf[1] >> 2 & =
0x1f);
> >
> > Why not just save rt_code in nvmem and you don't need to translate here=
?
> > If you need to do so, please add description for this.
> >
> > Regards,
> > Chun-Kuang.
> >
>
> Hi Chun-Kuang,
>
> The calibration data is flashed in rom when the IC FT test
> And the data struct can't be stored again

OK, it looks like this transtation is necessary.
If it's fixed, I would like to get the rt_code when probe or somewhere
initialization.

Regards,
Chun-Kuang.

>
> Best Regards
> JItao
> >
> > > +
> > > +       for (i =3D 0; i < 5; i++) {
> > > +               if ((rt_code[i] & 0x1f) =3D=3D 0)
> > > +                       rt_code[i] |=3D 0x10;
> > > +
> > > +               if ((rt_code[i] >> 5 & 0x1f) =3D=3D 0)
> > > +                       rt_code[i] |=3D 0x10 << 5;
> > > +
> > > +               for (j =3D 0; j < 10; j++)
> > > +                       mtk_mipi_tx_update_bits(mipi_tx,
> > > +                               MIPITX_D2P_RTCODE * (i + 1) + j * 4,
> > > +                               1, rt_code[i] >> j & 1);
> > > +       }
> > > +
> > > +       kfree(buf);
> > > +}
> > > +
> > >  static void mtk_mipi_tx_power_on_signal(struct phy *phy)
> > >  {
> > >         struct mtk_mipi_tx *mipi_tx =3D phy_get_drvdata(phy);
> > > @@ -130,6 +185,8 @@ static void mtk_mipi_tx_power_on_signal(struct ph=
y *phy)
> > >                                 RG_DSI_HSTX_LDO_REF_SEL,
> > >                                 (mipi_tx->mipitx_drive - 3000) / 200 =
<< 6);
> > >
> > > +       mtk_mipi_tx_config_calibration_data(mipi_tx);
> > > +
> > >         mtk_mipi_tx_set_bits(mipi_tx, MIPITX_CK_CKMODE_EN, DSI_CK_CKM=
ODE_EN);
> > >  }
> > >
> > > --
> > > 2.21.0
> > > _______________________________________________
> > > dri-devel mailing list
> > > dri-devel@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/dri-devel
>
>