Received: by 2002:a25:6193:0:0:0:0:0 with SMTP id v141csp3421137ybb; Mon, 6 Apr 2020 08:37:38 -0700 (PDT) X-Google-Smtp-Source: APiQypLEhPBxMIZSBK52TFHXIwvUNcrhmUYVxttw8p4HOrJBciznzG5iApjr6c4FRMxJzCS9fmKn X-Received: by 2002:aca:3783:: with SMTP id e125mr12549997oia.93.1586187457954; Mon, 06 Apr 2020 08:37:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1586187457; cv=none; d=google.com; s=arc-20160816; b=jjD1Lk5Vzy8b0DwUt7qG8SDiMtMldYOFa5lKWdAzoGkcWL9XVQ8cAdTMvd+wElT9Nu ihsun/H5KHyxRMWoG92XketNlUHXPTgV03oGM+j5bXm36V6njPT8alOJhYaxOTXRcjs0 rm3av9m/pz67at+8GPg7F2D+GxyeuYnrarnr0lg5LVSUxVVH5G0Q8AvQxNAJNzbQzOjg MNAmzLyR1bk0AabFy2yvzQ+DmihwUoGh21xSRCpgcMgJKVP3ar6hoHhgyZrp36Y8xqy1 GmT9eWwrc7RiH5/BR7Wj2hNqFTPZoaLOqToAjv91uKAyPfraz+J4URr4mJ23jSqeMh1f 8Ysg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:dkim-signature:content-language :content-transfer-encoding:in-reply-to:mime-version:user-agent:date :message-id:from:references:cc:to:subject; bh=5xUdeFe+tsnvL5IQpFJYpz5Hc6UjFOqVctZRzHoI4l8=; b=cajD6+QXbX7sUqWMySgIVhYYu165yx53s5K0SH18Mo8AgMfjfHC13RiBDcM7cOLabX adQAmjcs/8sNx65WlvQHaBOJPh0Ibd2TYtiEeBc328FeKNU2nKv+auWkcvU2IUsUwPnb xISxp3gY+q+33+oBiXLm0DlzBGmuSlCxWiumQ4pb3zBjqTJScC9eU4gFrsczJfAP/2K6 3IHwDYuyxpcKiDNHNMYPaCDZwicR5d4vFk8lY/nwUbGsdcTzTSjuAHvnLwctc4xQr0j4 5qmU+GbGb34PZW5dwBsAxy5RIpjQxq7OjXxOg8z2/zDjcR33PUkOjlrQQYMoxxIhvvah DKzw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=RoKNtoxE; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 5si7250599oin.43.2020.04.06.08.37.15; Mon, 06 Apr 2020 08:37:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=RoKNtoxE; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729050AbgDFPfr (ORCPT + 99 others); Mon, 6 Apr 2020 11:35:47 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:11346 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729039AbgDFPfr (ORCPT ); Mon, 6 Apr 2020 11:35:47 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 06 Apr 2020 08:35:32 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Mon, 06 Apr 2020 08:35:45 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Mon, 06 Apr 2020 08:35:45 -0700 Received: from DRHQMAIL107.nvidia.com (10.27.9.16) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 6 Apr 2020 15:35:45 +0000 Received: from [10.2.164.193] (10.124.1.5) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 6 Apr 2020 15:35:44 +0000 Subject: Re: [RFC PATCH v6 6/9] media: tegra: Add Tegra210 Video input driver To: Dmitry Osipenko , , , , , , CC: , , , , , References: <1585963507-12610-1-git-send-email-skomatineni@nvidia.com> <1585963507-12610-7-git-send-email-skomatineni@nvidia.com> <38d921a7-5cdf-8d0a-2772-4399dd1a96a0@gmail.com> From: Sowjanya Komatineni Message-ID: <9b8cf37b-d2ad-9df2-aad8-216c2c954e69@nvidia.com> Date: Mon, 6 Apr 2020 08:35:43 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <38d921a7-5cdf-8d0a-2772-4399dd1a96a0@gmail.com> X-Originating-IP: [10.124.1.5] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To DRHQMAIL107.nvidia.com (10.27.9.16) Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: quoted-printable Content-Language: en-US DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1586187332; bh=5xUdeFe+tsnvL5IQpFJYpz5Hc6UjFOqVctZRzHoI4l8=; h=X-PGP-Universal:Subject:To:CC:References:From:Message-ID:Date: User-Agent:MIME-Version:In-Reply-To:X-Originating-IP: X-ClientProxiedBy:Content-Type:Content-Transfer-Encoding: Content-Language; b=RoKNtoxE20Gnm62y7RzwoPimN0Vsf3JEhU7OkkkjnLgK5hI9vWg9l2FlR0O7eRGrc lddPB7iclnDsMrDeSyc/CU+vb2Ajzq6tBAyo9I9qLrCh2A60RJCi7DWsdvW2/t2/WJ o9WDqvYFk2ZrzU1/FcNlHFZf5xswGQaBaBofLt7m8ySt9iacd3CbKHSk8LgXduBv3t uBEasTaHe9f8fBjQ4gSVwgAwn4x8Xoj7UXCP3K1sFMbP7cy6Lvaf7h4VERsWqD5L6e kaWrruKHg3dY4jUf9kmqx3OzQjDt2mgiB0n6DY7jtE7iyZ31TPEr8/MIxsMHpQgSGu rFhLLUdLr9etw== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 4/5/20 1:35 PM, Dmitry Osipenko wrote: > External email: Use caution opening links or attachments > > > 04.04.2020 04:25, Sowjanya Komatineni =D0=BF=D0=B8=D1=88=D0=B5=D1=82: > ... >> +static int tegra_channel_capture_frame(struct tegra_vi_channel *chan, >> + struct tegra_channel_buffer *buf) >> +{ >> + int err =3D 0; >> + u32 thresh, value, frame_start, mw_ack_done; >> + int bytes_per_line =3D chan->format.bytesperline; >> + >> + /* program buffer address by using surface 0 */ >> + vi_csi_write(chan, TEGRA_VI_CSI_SURFACE0_OFFSET_MSB, >> + (u64)buf->addr >> 32); >> + vi_csi_write(chan, TEGRA_VI_CSI_SURFACE0_OFFSET_LSB, buf->addr); >> + vi_csi_write(chan, TEGRA_VI_CSI_SURFACE0_STRIDE, bytes_per_line); >> + >> + /* >> + * Tegra VI block interacts with host1x syncpt for synchronizing >> + * programmed condition of capture state and hardware operation. >> + * Frame start and Memory write acknowledge syncpts has their own >> + * FIFO of depth 2. >> + * >> + * Syncpoint trigger conditions set through VI_INCR_SYNCPT registe= r >> + * are added to HW syncpt FIFO and when the HW triggers, syncpt >> + * condition is removed from the FIFO and counter at syncpoint ind= ex >> + * will be incremented by the hardware and software can wait for >> + * counter to reach threshold to synchronize capturing frame with = the >> + * hardware capture events. >> + */ >> + >> + /* increase channel syncpoint threshold for FRAME_START */ >> + thresh =3D host1x_syncpt_incr_max(chan->frame_start_sp, 1); >> + >> + /* Program FRAME_START trigger condition syncpt request */ >> + frame_start =3D VI_CSI_PP_FRAME_START(chan->portno); >> + value =3D VI_CFG_VI_INCR_SYNCPT_COND(frame_start) | >> + host1x_syncpt_id(chan->frame_start_sp); >> + tegra_vi_write(chan, TEGRA_VI_CFG_VI_INCR_SYNCPT, value); >> + >> + /* increase channel syncpoint threshold for MW_ACK_DONE */ >> + buf->mw_ack_sp_thresh =3D host1x_syncpt_incr_max(chan->mw_ack_sp, = 1); >> + >> + /* Program MW_ACK_DONE trigger condition syncpt request */ >> + mw_ack_done =3D VI_CSI_MW_ACK_DONE(chan->portno); >> + value =3D VI_CFG_VI_INCR_SYNCPT_COND(mw_ack_done) | >> + host1x_syncpt_id(chan->mw_ack_sp); >> + tegra_vi_write(chan, TEGRA_VI_CFG_VI_INCR_SYNCPT, value); >> + >> + /* enable single shot capture */ >> + vi_csi_write(chan, TEGRA_VI_CSI_SINGLE_SHOT, SINGLE_SHOT_CAPTURE); >> + chan->capture_reqs++; >> + >> + /* wait for syncpt counter to reach frame start event threshold */ >> + err =3D host1x_syncpt_wait(chan->frame_start_sp, thresh, >> + TEGRA_VI_SYNCPT_WAIT_TIMEOUT, &value); >> + if (err) { >> + dev_err(&chan->video.dev, >> + "frame start syncpt timeout: %d\n", err); >> + /* increment syncpoint counter for timedout events */ >> + host1x_syncpt_incr(chan->frame_start_sp); > Why incrementing is done while hardware is still active? > > The sync point's state needs to be completely reset after resetting > hardware. But I don't think that the current upstream host1x driver > supports doing that, it's one of the known-long-standing problems of the > host1x driver. > > At least the sp->max_val incrementing should be done based on the actual > syncpoint value and this should be done after resetting hardware. upstream host1x driver don't have API to reset or to equalize max value=20 with min/load value. So to synchronize missed event, incrementing HW syncpt counter. This should not impact as we increment this in case of missed events only. >> + spin_lock(&chan->sp_incr_lock); >> + host1x_syncpt_incr(chan->mw_ack_sp); >> + spin_unlock(&chan->sp_incr_lock); >> + /* clear errors and recover */ >> + tegra_channel_capture_error_recover(chan); >> + release_buffer(chan, buf, VB2_BUF_STATE_ERROR); >> + return err; >> + }