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<9038ce90-ac53-93e7-ce65-57f6ff1e9b30@nvidia.com> From: Sowjanya Komatineni Message-ID: <36b5627a-8639-6244-8620-4f23828e0638@nvidia.com> Date: Mon, 6 Apr 2020 13:05:42 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: X-Originating-IP: [10.124.1.5] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To DRHQMAIL107.nvidia.com (10.27.9.16) Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: quoted-printable Content-Language: en-US DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1586203443; bh=/cQeQIFkotsxVl4iOAXgB7AypQjT4YsAA1hb19W7EoY=; h=X-PGP-Universal:Subject:To:CC:References:From:Message-ID:Date: User-Agent:MIME-Version:In-Reply-To:X-Originating-IP: X-ClientProxiedBy:Content-Type:Content-Transfer-Encoding: Content-Language; b=LJRaJOIkLv6YKhIRIfeTh+coVu/yi4RULJDCuKHuc5G7ydBH0pTlTgPX09GwKSw/N 7busPDL5R0eOzF3zX82nUdrtwTU4zo5xNOnl79u2aZPi5aZQkxjmxp2S6htrvZ8U8C RYm6gjNqGAwgFYBwjc3lAelcwkWX++ayI1N4wOE/Tj7r8hRd7Dq08DV8vshkggOY6d QNlVQx8D1DO/sBUQbgMhN7uVIS8Oq6CNwy+Nl4/2MiUUYL0kTWbECP0vNf8QXauWpP E9af5mWqT3EHet7lgpG0Uixtia9TqyhZ0y1dl6/bfRkircQODDGV53OYIvoVCapRLv kpO7/pyF7q83g== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 4/6/20 12:53 PM, Dmitry Osipenko wrote: > External email: Use caution opening links or attachments > > > 06.04.2020 20:02, Sowjanya Komatineni =D0=BF=D0=B8=D1=88=D0=B5=D1=82: >> On 4/6/20 9:37 AM, Sowjanya Komatineni wrote: >>> On 4/6/20 9:29 AM, Dmitry Osipenko wrote: >>>> External email: Use caution opening links or attachments >>>> >>>> >>>> 06.04.2020 19:12, Sowjanya Komatineni =D0=BF=D0=B8=D1=88=D0=B5=D1=82: >>>>> On 4/6/20 9:05 AM, Dmitry Osipenko wrote: >>>>>> External email: Use caution opening links or attachments >>>>>> >>>>>> >>>>>> 06.04.2020 18:35, Sowjanya Komatineni =D0=BF=D0=B8=D1=88=D0=B5=D1=82= : >>>>>> ... >>>>>>>>> + /* wait for syncpt counter to reach frame start event >>>>>>>>> threshold */ >>>>>>>>> + err =3D host1x_syncpt_wait(chan->frame_start_sp, thresh, >>>>>>>>> + TEGRA_VI_SYNCPT_WAIT_TIMEOUT, &value); >>>>>>>>> + if (err) { >>>>>>>>> + dev_err(&chan->video.dev, >>>>>>>>> + "frame start syncpt timeout: %d\n", err); >>>>>>>>> + /* increment syncpoint counter for timedout events = */ >>>>>>>>> + host1x_syncpt_incr(chan->frame_start_sp); >>>>>>>> Why incrementing is done while hardware is still active? >>>>>>>> >>>>>>>> The sync point's state needs to be completely reset after resettin= g >>>>>>>> hardware. But I don't think that the current upstream host1x drive= r >>>>>>>> supports doing that, it's one of the known-long-standing problems = of >>>>>>>> the >>>>>>>> host1x driver. >>>>>>>> >>>>>>>> At least the sp->max_val incrementing should be done based on the >>>>>>>> actual >>>>>>>> syncpoint value and this should be done after resetting hardware. >>>>>>> upstream host1x driver don't have API to reset or to equalize max >>>>>>> value >>>>>>> with min/load value. >>>>>>> >>>>>>> So to synchronize missed event, incrementing HW syncpt counter. >>>>>>> >>>>>>> This should not impact as we increment this in case of missed event= s >>>>>>> only. >>>>>> It's wrong to touch sync point while hardware is active and it's >>>>>> active >>>>>> until being reset. >>>>>> >>>>>> You should re-check the timeout after hw resetting and manually put >>>>>> the >>>>>> syncpoint counter back into sync only if needed. >>>>> There is possibility of timeout to happen any time even during the >>>>> capture also and is not related to hw reset. >>>>> >>>>> Manual synchronization is needed when timeout of any frame events >>>>> happen >>>>> otherwise all subsequence frames will timeout due to mismatch in even= t >>>>> counters. >>>> My point is that hardware is stopped only after being reset, until the= n >>>> you should assume that sync point could be incremented by HW at any >>>> time. >>>> >>>> And if this happens that HW increments sync point after the timeout, >>>> then the sync point counter should become out-of-sync in yours case, >>>> IIUC. Because host1x_syncpt_incr() doesn't update the cached counter. >>> We wait for enough time based on frame rate for syncpt increment to >>> happen and if it doesn't happen by then definitely its missed event >>> and we increment HW syncpoint for this timed event. >>> >>> cached value gets updated during syncpt wait for subsequent event. >>> >>> syncpt increment happens for all subsequent frame events during video >>> capture. >>> >> Just to be clear, syncpt max value increment happens first and syncpt >> trigger condition is programmed. hw syncpt increment happens based on HW >> events. >> >> Wait time for HW syncpt to reach threshold is tuned to work for all >> frame rates. So if increment doesn't happen by then, its definitely >> missed event. > This is questionable. Technically, speculating about whether the tuned > value is good for all possible cases is incorrect thing to do. > > Although, I guess in practice it should be good enough for the starter > and could be improved later on, once the host1x driver will be improved. By tuned value I meant about 200ms wait timeout for frame event to=20 happen is what we have been using in downstream and with BSP release=20 images which works good for all sensors and bridges we supported so far. > >> In case of missed HW event corresponding to syncpt condition, hw syncpt >> increment does not happen and driver increments it on timeout. >> >> As there is not API to equialize max with min incase of timeout/reset, >> incrementing HW syncpt for timed out event. >> >> syncpt cached value gets updated during syncpt wait when it loads from >> HW syncpt. >> >> As syncpt condition is already triggered, without compensating timeout >> events or leaving syncpt max and hw syncpt in non synchronized state for >> missed events, subsequent streamings will all timeout even on real event= s. >>