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Subject: Re: [PATCH 0/6] Introduce ID_PFR2 and other CPU feature changes
To:     Will Deacon <will@kernel.org>
Cc:     linux-arm-kernel@lists.infradead.org,
        Catalin Marinas <catalin.marinas@arm.com>,
        Marc Zyngier <maz@kernel.org>,
        James Morse <james.morse@arm.com>,
        Suzuki K Poulose <suzuki.poulose@arm.com>,
        Mark Rutland <mark.rutland@arm.com>,
        kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org
References: <1580215149-21492-1-git-send-email-anshuman.khandual@arm.com>
 <20200406170911.GA7446@willie-the-truck>
From:   Anshuman Khandual <anshuman.khandual@arm.com>
Message-ID: <05f6eb1e-a82c-bd02-1871-e44ea00683d8@arm.com>
Date:   Tue, 7 Apr 2020 14:20:20 +0530
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On 04/06/2020 10:39 PM, Will Deacon wrote:
> On Tue, Jan 28, 2020 at 06:09:03PM +0530, Anshuman Khandual wrote:
>> This series is primarily motivated from an adhoc list from Mark Rutland
>> during our ID_ISAR6 discussion [1]. Besides, it also includes a patch
>> which does macro replacement for various open bits shift encodings in
>> various CPU ID registers. This series is based on linux-next 20200124.
>>
>> [1] https://patchwork.kernel.org/patch/11287805/
>>
>> Is there anything else apart from these changes which can be accommodated
>> in this series, please do let me know. Thank you.
> 
> The latest Arm ARM also talks about DFR1 and MMFR5. Please can you include

Sure, will do.

> those too? Might also be worth checking to see if anything is missing on
> the 64-bit side as well (I didn't look).

Yeah. Now there some missing ones, will add those as well.

> 
> Will
>