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From:   Jiaxun Yang <jiaxun.yang@flygoat.com>
To:     linux-mips@vger.kernel.org
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Message-ID: <20200408113505.2528103-3-jiaxun.yang@flygoat.com>
Subject: [PATCH 02/12] MIPS: prom: Add helper to parse CPU node in dt
Date:   Wed,  8 Apr 2020 19:34:12 +0800
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Mostly identical with arm one. The only difference is that we allow
to mark a CPU Node as status =3D "disabled" in dt, which means the core
is physicaly present, but not possible for the kernel. It will occupy
a bit in cpumask as well.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 arch/mips/include/asm/prom.h |  2 +
 arch/mips/kernel/prom.c      | 96 ++++++++++++++++++++++++++++++++++++
 2 files changed, 98 insertions(+)

diff --git a/arch/mips/include/asm/prom.h b/arch/mips/include/asm/prom.h
index c42e07671934..1ec46e09dc8b 100644
--- a/arch/mips/include/asm/prom.h
+++ b/arch/mips/include/asm/prom.h
@@ -19,9 +19,11 @@ struct boot_param_header;
=20
 extern void __dt_setup_arch(void *bph);
 extern int __dt_register_buses(const char *bus0, const char *bus1);
+extern void mips_dt_init_cpu_maps(void);
=20
 #else /* CONFIG_OF */
 static inline void device_tree_init(void) { }
+static inline void mips_dt_init_cpu_maps(void) { }
 #endif /* CONFIG_OF */
=20
 extern char *mips_get_machine_name(void);
diff --git a/arch/mips/kernel/prom.c b/arch/mips/kernel/prom.c
index 9e50dc8df2f6..ebeb22ffa76a 100644
--- a/arch/mips/kernel/prom.c
+++ b/arch/mips/kernel/prom.c
@@ -89,4 +89,100 @@ int __init __dt_register_buses(const char *bus0, const =
char *bus1)
 =09return 0;
 }
=20
+void __init mips_dt_init_cpu_maps(void)
+{
+=09struct device_node *cpu, *cpus;
+=09u32 i, j, cpuidx =3D 1;
+=09u32 cpunum;
+=09u32 tmp_map[NR_CPUS] =3D { [0 ... NR_CPUS-1] =3D U32_MAX };
+=09bool cpu_possible[NR_CPUS] =3D { [0 ... NR_CPUS-1] =3D false };
+=09bool bootcpu_valid =3D false;
+
+=09cpus =3D of_find_node_by_path("/cpus");
+=09if (!cpus)
+=09=09return;
+
+=09if (cpu_has_mips_r2_r6)
+=09=09cpunum =3D get_ebase_cpunum();
+=09else
+=09=09cpunum =3D 0; /* For legacy system we assume boot from CPU 0 */
+
+=09for_each_of_cpu_node(cpu) {
+=09=09u32 hwid;
+
+=09=09pr_debug(" * %pOF...\n", cpu);
+=09=09/*
+=09=09 * A device tree containing CPU nodes with missing "reg"
+=09=09 * properties is considered invalid to build the
+=09=09 * cpu_logical_map.
+=09=09 */
+
+=09=09if (of_property_read_u32(cpu, "reg", &hwid)) {
+=09=09=09pr_debug(" * %pOF missing reg property\n", cpu);
+=09=09=09of_node_put(cpu);
+=09=09=09return;
+=09=09}
+
+=09=09/*
+=09=09 * Duplicate hwid are a recipe for disaster.
+=09=09 * Scan all initialized entries and check for
+=09=09 * duplicates. If any is found just bail out.
+=09=09 */
+=09=09for (j =3D 0; j < cpuidx; j++)
+=09=09=09if (WARN(tmp_map[j] =3D=3D hwid,
+=09=09=09=09 "Duplicate /cpu reg properties in the DT\n")) {
+=09=09=09=09of_node_put(cpu);
+=09=09=09=09return;
+=09=09=09}
+
+=09=09/*
+=09=09 * Build a stashed array of hwid values. Numbering scheme
+=09=09 * requires that if detected the boot CPU must be assigned
+=09=09 * logical id 0. Other CPUs get sequential indexes starting
+=09=09 * from 1. If a CPU node with a reg property matching the
+=09=09 * boot CPU hwid is detected, this is recorded so that the
+=09=09 * logical map built from DT is validated.
+=09=09 */
+=09=09if (hwid =3D=3D cpunum) {
+=09=09=09i =3D 0;
+=09=09=09if (of_device_is_available(cpu))
+=09=09=09=09bootcpu_valid =3D true;
+=09=09} else {
+=09=09=09i =3D cpuidx++;
+=09=09}
+
+=09=09if (WARN(cpuidx > nr_cpu_ids, "DT /cpu %u nodes greater than "
+=09=09=09=09=09=09   "max cores %u, capping them\n",
+=09=09=09=09=09=09   cpuidx, nr_cpu_ids)) {
+=09=09=09cpuidx =3D nr_cpu_ids;
+=09=09=09of_node_put(cpu);
+=09=09=09break;
+=09=09}
+
+=09=09tmp_map[i] =3D hwid;
+
+=09=09if (of_device_is_available(cpu))
+=09=09=09cpu_possible[i] =3D true;
+=09}
+
+=09if (!bootcpu_valid) {
+=09=09pr_warn("DT missing boot CPU, fall back to default cpu_logical_map\n=
");
+=09=09return;
+=09}
+
+=09init_cpu_possible(cpu_none_mask);
+=09init_cpu_present(cpu_none_mask);
+
+=09for (i =3D 0; i < cpuidx; i++) {
+=09=09set_cpu_possible(i, cpu_possible[i]);
+=09=09cpu_logical_map(i) =3D tmp_map[i];
+=09=09pr_debug("cpu logical map 0x%x\n", cpu_logical_map(i));
+=09}
+}
+
+bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
+{
+=09return phys_id =3D=3D cpu_logical_map(cpu);
+}
+
 #endif
--=20
2.26.0.rc2