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Subject: Re: [PATCH v2] arm64: dts: mt8173: Add gce setting in mmsys and
 display node
To:     Hsin-Yi Wang <hsinyi@chromium.org>,
        linux-arm-kernel@lists.infradead.org
Cc:     Rob Herring <robh+dt@kernel.org>, devicetree@vger.kernel.org,
        linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org,
        Chun-Kuang Hu <chunkuang.hu@kernel.org>,
        Enric Balletbo i Serra <enric.balletbo@collabora.com>
References: <20200409055012.199320-1-hsinyi@chromium.org>
From:   Matthias Brugger <matthias.bgg@gmail.com>
Message-ID: <032911c9-ba57-4586-969b-90358be19a10@gmail.com>
Date:   Mon, 13 Apr 2020 14:11:01 +0200
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On 4/9/20 7:50 AM, Hsin-Yi Wang wrote:
> In order to use GCE function, we need add some informations
> into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events=
).
>=20
> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
> Reviewed-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> ---

Applied to v5.7-next/dts64

Thanks!

> change log:
> v1->v2: align with
> 19d8e335d58a ("dt-binding: gce: remove atomic_exec in mboxes property")=

> 60fa8c13ab1a ("drm/mediatek: Move gce event property to mutex device no=
de")
> ---
>  arch/arm64/boot/dts/mediatek/mt8173.dtsi | 18 +++++++++++++++++-
>  1 file changed, 17 insertions(+), 1 deletion(-)
>=20
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot=
/dts/mediatek/mt8173.dtsi
> index ccb8e88a60c5..8337ba42845d 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> @@ -549,7 +549,7 @@ gce: mailbox@10212000 {
>  			interrupts =3D <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
>  			clocks =3D <&infracfg CLK_INFRA_GCE>;
>  			clock-names =3D "gce";
> -			#mbox-cells =3D <3>;
> +			#mbox-cells =3D <2>;
>  		};
> =20
>  		mipi_tx0: mipi-dphy@10215000 {
> @@ -916,6 +916,9 @@ mmsys: clock-controller@14000000 {
>  			assigned-clocks =3D <&topckgen CLK_TOP_MM_SEL>;
>  			assigned-clock-rates =3D <400000000>;
>  			#clock-cells =3D <1>;
> +			mboxes =3D <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
> +				 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
> +			mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0 0x1000>;
>  		};
> =20
>  		mdp_rdma0: rdma@14001000 {
> @@ -996,6 +999,7 @@ ovl0: ovl@1400c000 {
>  			clocks =3D <&mmsys CLK_MM_DISP_OVL0>;
>  			iommus =3D <&iommu M4U_PORT_DISP_OVL0>;
>  			mediatek,larb =3D <&larb0>;
> +			mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
>  		};
> =20
>  		ovl1: ovl@1400d000 {
> @@ -1006,6 +1010,7 @@ ovl1: ovl@1400d000 {
>  			clocks =3D <&mmsys CLK_MM_DISP_OVL1>;
>  			iommus =3D <&iommu M4U_PORT_DISP_OVL1>;
>  			mediatek,larb =3D <&larb4>;
> +			mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
>  		};
> =20
>  		rdma0: rdma@1400e000 {
> @@ -1016,6 +1021,7 @@ rdma0: rdma@1400e000 {
>  			clocks =3D <&mmsys CLK_MM_DISP_RDMA0>;
>  			iommus =3D <&iommu M4U_PORT_DISP_RDMA0>;
>  			mediatek,larb =3D <&larb0>;
> +			mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
>  		};
> =20
>  		rdma1: rdma@1400f000 {
> @@ -1026,6 +1032,7 @@ rdma1: rdma@1400f000 {
>  			clocks =3D <&mmsys CLK_MM_DISP_RDMA1>;
>  			iommus =3D <&iommu M4U_PORT_DISP_RDMA1>;
>  			mediatek,larb =3D <&larb4>;
> +			mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
>  		};
> =20
>  		rdma2: rdma@14010000 {
> @@ -1036,6 +1043,7 @@ rdma2: rdma@14010000 {
>  			clocks =3D <&mmsys CLK_MM_DISP_RDMA2>;
>  			iommus =3D <&iommu M4U_PORT_DISP_RDMA2>;
>  			mediatek,larb =3D <&larb4>;
> +			mediatek,gce-client-reg =3D <&gce SUBSYS_1401XXXX 0 0x1000>;
>  		};
> =20
>  		wdma0: wdma@14011000 {
> @@ -1046,6 +1054,7 @@ wdma0: wdma@14011000 {
>  			clocks =3D <&mmsys CLK_MM_DISP_WDMA0>;
>  			iommus =3D <&iommu M4U_PORT_DISP_WDMA0>;
>  			mediatek,larb =3D <&larb0>;
> +			mediatek,gce-client-reg =3D <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
>  		};
> =20
>  		wdma1: wdma@14012000 {
> @@ -1056,6 +1065,7 @@ wdma1: wdma@14012000 {
>  			clocks =3D <&mmsys CLK_MM_DISP_WDMA1>;
>  			iommus =3D <&iommu M4U_PORT_DISP_WDMA1>;
>  			mediatek,larb =3D <&larb4>;
> +			mediatek,gce-client-reg =3D <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
>  		};
> =20
>  		color0: color@14013000 {
> @@ -1064,6 +1074,7 @@ color0: color@14013000 {
>  			interrupts =3D <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains =3D <&scpsys MT8173_POWER_DOMAIN_MM>;
>  			clocks =3D <&mmsys CLK_MM_DISP_COLOR0>;
> +			mediatek,gce-client-reg =3D <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
>  		};
> =20
>  		color1: color@14014000 {
> @@ -1072,6 +1083,7 @@ color1: color@14014000 {
>  			interrupts =3D <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains =3D <&scpsys MT8173_POWER_DOMAIN_MM>;
>  			clocks =3D <&mmsys CLK_MM_DISP_COLOR1>;
> +			mediatek,gce-client-reg =3D <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
>  		};
> =20
>  		aal@14015000 {
> @@ -1080,6 +1092,7 @@ aal@14015000 {
>  			interrupts =3D <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains =3D <&scpsys MT8173_POWER_DOMAIN_MM>;
>  			clocks =3D <&mmsys CLK_MM_DISP_AAL>;
> +			mediatek,gce-client-reg =3D <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
>  		};
> =20
>  		gamma@14016000 {
> @@ -1088,6 +1101,7 @@ gamma@14016000 {
>  			interrupts =3D <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains =3D <&scpsys MT8173_POWER_DOMAIN_MM>;
>  			clocks =3D <&mmsys CLK_MM_DISP_GAMMA>;
> +			mediatek,gce-client-reg =3D <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
>  		};
> =20
>  		merge@14017000 {
> @@ -1193,6 +1207,8 @@ mutex: mutex@14020000 {
>  			interrupts =3D <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains =3D <&scpsys MT8173_POWER_DOMAIN_MM>;
>  			clocks =3D <&mmsys CLK_MM_MUTEX_32K>;
> +			mediatek,gce-events =3D <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
> +                                              <CMDQ_EVENT_MUTEX1_STREA=
M_EOF>;
>  		};
> =20
>  		larb0: larb@14021000 {
>=20