Message-ID: <440494FC.9050400@nortel.com>
Date: Tue, 28 Feb 2006 12:22:52 -0600
From: "Christopher Friesen" <cfriesen@nortel.com>
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To: Benjamin LaHaise <bcrl@kvack.org>
CC: "Bryan O'Sullivan" <bos@pathscale.com>, Andrew Morton <akpm@osdl.org>,
       Andi Kleen <ak@suse.de>, linux-kernel <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] Define wc_wmb, a write barrier for PCI write combining
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Benjamin LaHaise wrote:
> On Tue, Feb 28, 2006 at 09:50:08AM -0800, Bryan O'Sullivan wrote:
> 
>>The last 32-bit write triggers the chip to put the packet on the wire.
>>We make sure it happens after the earlier bulk write using a barrier.
> 
> 
> The barrier you're looking for is wmb() in asm/system.h, which is defined 
> on both SMP and UP.

That will synchronize with other CPUs as well, which may not necessarily 
be needed.

On PPC for instance, you could implement the desired semantics using 
"eieio" (enforce in-order execution of IO).  This is lighter weight than 
a full "sync", which is what wmb() maps to.

Chris
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