Received: by 2002:a25:1985:0:0:0:0:0 with SMTP id 127csp138400ybz; Wed, 15 Apr 2020 06:03:54 -0700 (PDT) X-Google-Smtp-Source: APiQypLbY9+2GKM7LKDgHnSTK7Ki5+K8/fkKp1j3ESZ17fmmk1kvuV5rJhFy4tqlBXmPJlDvQIPC X-Received: by 2002:a17:906:29c4:: with SMTP id y4mr4890357eje.95.1586955833823; Wed, 15 Apr 2020 06:03:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1586955833; cv=none; d=google.com; s=arc-20160816; b=bHYTusYe6XySjczx84qIE3jnKDAt0xrfhdb+dND6bvM99R0S5ME7sIpF31e5RLGLDA znvb79HFEX3ll6GYWSt2YR6RXABInj1OTwrDbuUtqA5pLREQ+9bsgMrzces7jRhIF9/I E7GiZUa8DfAfK94Qt7fRAAKGZB20p7XxVX7Chp+5XnbigpjdmnH2+G+bphsAUi0J22tu busFT595DIp+ncMBKlPYrYlKN7z5CdcCmofTq3OibnIjgNUbrdctQjA4UY7FZ2K63xLY 95l6rerIdkHw4CGJnWhJd+zkXeQD0bQbOOEYRIGPt6LZVYI7sbxmFrLR6Nfq6y/lxUot SpkQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:dkim-signature; bh=VclBjPf0G+5Fbq0gaSlTkJ1trKfc494vLUCcFmtZb4c=; b=VUyD82RllRstTY1HPM5u8X8y8Y57zRWxWlorxsAD5mv9JbxMYyJXwvP4itc4/0d3Rl ciQWZNCABKEhn3+h6la2gbyQ0wqT7cWwfrID41tIplUmSMiVK1Go1s2pyq71hRusCqZa ttHBmyB1VkRr1sHh15zVoobK6zbL0KqiOKJ0CIvJLV1ZwvuIbE9WWWtZEblK2152L/0h fZVqjvE2FZUPehVq9WYH9r1VOYo3u7IPzrN+27/QlET8/gLUYU8dOCvECOJyp/JUfC2B I1KrsFqpi5P3oZIs4pKRgUYD6NkfqYHc2ANcsDs9iaL3L3qn2wnUdHgHBA1AMP/qAyHV F4kA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=PsNiBJat; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id i11si11466239eds.272.2020.04.15.06.03.23; Wed, 15 Apr 2020 06:03:53 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=PsNiBJat; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2503704AbgDNSPT (ORCPT + 99 others); Tue, 14 Apr 2020 14:15:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45696 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S2503671AbgDNSPQ (ORCPT ); Tue, 14 Apr 2020 14:15:16 -0400 Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0862EC061A0C for ; Tue, 14 Apr 2020 11:15:16 -0700 (PDT) Received: by mail-wm1-x342.google.com with SMTP id e26so14141519wmk.5 for ; Tue, 14 Apr 2020 11:15:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=VclBjPf0G+5Fbq0gaSlTkJ1trKfc494vLUCcFmtZb4c=; b=PsNiBJat77NUlKls3n38NeJLDYLaxdO6QQ6kNr7NquUmAWTr4Xr/gyZ+hbFWU/eXM7 2RULAsbItfI/aUioDQWzlNzU9OwRPaWk6JkOzaTreyYLviOdSSY453B7dw+PDBDHSt5F x+ojvn8taK7Eh5VzTxRhgWytqULvg+MjLbTb5qPvwe3GT/SM9ICpx465II+ZHxlvDEu6 EdZu5PKeyOnl92lAJp0VvmNLIhz/DfFnnJXqACQ6ap+4a4nM1nzV/2vePaF6OLLpoPp6 VhB8C6nOdPPLhz3JyOYIeW/DRBlSu3OAR06M2NqGsi/j9hp5y8zxBDFL/blKkRX+TQ3S +mhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=VclBjPf0G+5Fbq0gaSlTkJ1trKfc494vLUCcFmtZb4c=; b=Nc6mw3v1GmuQppj7NwgEnkkajyIeNLB0redkdQBB9MtIEwBNuIKpKMMupI6gfjj9sO qE8nyU9ro4KulLkInGyHq/xUctljn0DTUJlo8+APDCToxzNFpXxy8ag6gUPb9RIjNZVx qOV2/iCG/I19bZsHt29GgSHk/oSZFR/f4zc9dSoY5+uM5Z4hk0l6BKGU6lo1HVZJhUfP i2OR6850oDC26VuxhLPS3mtfpd/73FAFZvv5fAKOMw8Nv3wf3LForLhLXyBZLRQ/PpwD EZRp/CzZ/1aTN7mTqosliGjNd3PnRy7w7BZMXWrbwl4OBNvj9+KpETa5j829rwJ5rnCO j4GA== X-Gm-Message-State: AGi0PuZbd1TSsDJNRKMobl5WcmoSoBsY/hm1QbcjYvs5n9aBYqQpPA3f joAdccvWP+9GSiPAL5I9CQh/V9I25rynBLdj9DI= X-Received: by 2002:a1c:6344:: with SMTP id x65mr1101168wmb.56.1586888114753; Tue, 14 Apr 2020 11:15:14 -0700 (PDT) MIME-Version: 1.0 References: <1586864113-30682-1-git-send-email-bernard@vivo.com> In-Reply-To: <1586864113-30682-1-git-send-email-bernard@vivo.com> From: Alex Deucher Date: Tue, 14 Apr 2020 14:15:03 -0400 Message-ID: Subject: Re: [PATCH] Optimized division operation to shift operation To: Bernard Zhao Cc: Alex Deucher , =?UTF-8?Q?Christian_K=C3=B6nig?= , "David (ChunMing) Zhou" , David Airlie , Daniel Vetter , Felix Kuehling , Xiaojie Yuan , Oak Zeng , Sam Ravnborg , Alex Sierra , Huang Rui , Kent Russell , amd-gfx list , Maling list - DRI developers , LKML , kernel@vivo.com Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Apr 14, 2020 at 9:05 AM Bernard Zhao wrote: > > On some processors, the / operate will call the compiler`s div lib, > which is low efficient, We can replace the / operation with shift, > so that we can replace the call of the division library with one > shift assembly instruction. > > Signed-off-by: Bernard Zhao Applied. thanks. Alex > --- > drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 4 ++-- > drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 4 ++-- > drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 4 ++-- > 3 files changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c > index b205039..66cd078 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c > @@ -175,10 +175,10 @@ static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev) > amdgpu_ucode_print_mc_hdr(&hdr->header); > > adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); > - regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); > + regs_size = le32_to_cpu(hdr->io_debug_size_bytes) >> 3; > new_io_mc_regs = (const __le32 *) > (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); > - ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; > + ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) >> 2; > new_fw_data = (const __le32 *) > (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); > > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c > index 9da9596..ca26d63 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c > @@ -193,10 +193,10 @@ static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev) > amdgpu_ucode_print_mc_hdr(&hdr->header); > > adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); > - regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); > + regs_size = le32_to_cpu(hdr->io_debug_size_bytes) >> 3; > io_mc_regs = (const __le32 *) > (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); > - ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; > + ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) >> 2; > fw_data = (const __le32 *) > (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); > > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c > index 27d83204..295039c 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c > @@ -318,10 +318,10 @@ static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev) > amdgpu_ucode_print_mc_hdr(&hdr->header); > > adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); > - regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); > + regs_size = le32_to_cpu(hdr->io_debug_size_bytes) >> 3; > io_mc_regs = (const __le32 *) > (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); > - ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; > + ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) >> 2; > fw_data = (const __le32 *) > (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); > > -- > 2.7.4 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx