From: Andi Kleen <ak@suse.de>
To: "Bryan O'Sullivan" <bos@pathscale.com>
Subject: Re: [PATCH] Define wc_wmb, a write barrier for PCI write combining
Date: Tue, 28 Feb 2006 20:33:47 +0100
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On Tuesday 28 February 2006 20:20, Bryan O'Sullivan wrote:

> We added the memory barrier to *improve* performance, in addition to
> helping correctness and portability.  Without it, the CPU or north
> bridge is free to hold onto the pending writes for a while; the exact
> details of how long it will wait depend on the CPU and NB
> implementation, but on AMD64 CPUs the delay is up to 16 cycles.

Are you sure you used the right instruction? Normally CLFLUSH is used
for such things, not a write barrier which really only changes ordering.
The documentation is not fully clear, but it sounds like it could
apply to the store buffers too.

Anyways if MFENCE improved performance you're probably relying
on some very specific artifact of the microarchitecture of your 
CPU or Northbridge. I don't think it's a architecurally guaranteed
feature.
 
-Andi
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