Received: by 2002:a25:1985:0:0:0:0:0 with SMTP id 127csp241855ybz; Wed, 15 Apr 2020 07:57:28 -0700 (PDT) X-Google-Smtp-Source: APiQypJvTfscgQBTHaT/G1H9Da1iBNPuhsQD/wq7C0YcP/pSnymMKkn/OubdWWrbPuxb9sIwh9z3 X-Received: by 2002:aa7:d64e:: with SMTP id v14mr15283247edr.19.1586962648613; Wed, 15 Apr 2020 07:57:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1586962648; cv=none; d=google.com; s=arc-20160816; b=hC0Qpbcn9Gl+PSKzMaaY8Ga6AKzNLfwSYSI1Jb/ULFKrMWeVut7qtstjwB9qn9OAj+ eTKLQadxqEtEaPFRU4ZpIL2Io2H4SxD7iZPkQsrMKIZnT94B97ILE475Uz2akUSbf1xK rVyLpW1uDjW2bMFDxGB44OqIgSmyoeoriRPb4zIH2P597B+Mg/tAS2wN22cezO2iTbu8 fWeuR6X+/1PP9xlrg3sTmFfd56SiRJjRxxmt9HQZzfRaAu+C2GDCg3GDZUa5PZPBiX/s HSoeHH+JrCKvjdRlkCJ0b0t6B18mAOk7yWWkvhImPC4E0+I69a+9C2Ei/0Qms4hkA36R jnSA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:dkim-signature:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from; bh=/06MYnopqzjyrf2N0nRAUhGBnkcd6r/kBjlHyehzo9I=; b=JLbprqTIOpQHHSH5lKkJoqMtvnGl9BLRyPgtE1yTYMS9M0YYapDLk90sJLfc31wIEE 3DIhLV7+pgBsVCA2EiqoEqph8BjfNb7bczBxXbrEl6jV+I3L3YgUOkXdKYx3PVRipkns Cx/MlLcsyZOf9rRVnFjIUkV90OYrvZqDPyL4tKMrGGpazJy1dvjPrhD1t5fUqg7haly5 t+qyVxw8F/WwU4dxG4rwzLmxnbh+DZHkTYlDRXmR5FoUPHtVOzJSbBbbEhQhonYBpfW+ dFXXBlNcX0C4Q/6THi4fjaOZZQZmsu4rK8KAGaBOTMEiIr5t5jYq7flvcGOmyzeTMs/E S0/w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b="rDd/7f6S"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id ks15si5007531ejb.223.2020.04.15.07.57.04; Wed, 15 Apr 2020 07:57:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b="rDd/7f6S"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729709AbgDOC6e (ORCPT + 99 others); Tue, 14 Apr 2020 22:58:34 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:3768 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728671AbgDOC5w (ORCPT ); Tue, 14 Apr 2020 22:57:52 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 14 Apr 2020 19:56:50 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 14 Apr 2020 19:57:48 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 14 Apr 2020 19:57:48 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 15 Apr 2020 02:57:48 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 15 Apr 2020 02:57:48 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.171.241]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 14 Apr 2020 19:57:48 -0700 From: Sowjanya Komatineni To: , , , , , , CC: , , , , , , Subject: [RFC PATCH v7 4/9] clk: tegra: Add Tegra210 CSI TPG clock gate Date: Tue, 14 Apr 2020 19:57:38 -0700 Message-ID: <1586919463-30542-5-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1586919463-30542-1-git-send-email-skomatineni@nvidia.com> References: <1586919463-30542-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1586919410; bh=/06MYnopqzjyrf2N0nRAUhGBnkcd6r/kBjlHyehzo9I=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=rDd/7f6Suh9mmisKphr+X2KO6ruiJ6ZTLWX3BH3+/kxfUXwtpR0Y9QDwYTlScgsLr 0dawAxCrd+sqSGmKpGyOfTV2Erlrl2SlgD7yIuz7MsXiVxE5uQ0f9V+HDaxniPsIxA LcDCGAblUvtqycfcEYTHHr/piTWWy0JhJvKrC0teR/6xFdrd24OR9jgv3BLpp2zzQ8 E2U0X9XV8RKxxy18fcAG6cob+BSi3uap30rFeVFuno4xMxVLYGCr8RllL0aKwYgP86 TksnFdicdQjtqazGq54x6sNDSKFcGCu/gLeLbiNGskA2isf0KGFF4BDtBdAaSNLxz9 U7KJviVALddcA== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Tegra210 CSI hardware internally uses PLLD for internal test pattern generator logic. PLLD_BASE register in CAR has a bit CSI_CLK_SOURCE to enable PLLD out to CSI during TPG mode. This patch adds this CSI TPG clock gate to Tegra210 clock driver to allow Tegra video driver to ungate CSI TPG clock during TPG mode and gate during non TPG mode. Acked-by: Stephen Boyd Signed-off-by: Sowjanya Komatineni --- drivers/clk/tegra/clk-tegra210.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index defe3b7..81a879b 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -3035,6 +3035,13 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base, periph_clk_enb_refcnt); clks[TEGRA210_CLK_DSIB] = clk; + /* csi_tpg */ + clk = clk_register_gate(NULL, "csi_tpg", "pll_d", + CLK_SET_RATE_PARENT, clk_base + PLLD_BASE, + 23, 0, &pll_d_lock); + clk_register_clkdev(clk, "csi_tpg", NULL); + clks[TEGRA210_CLK_CSI_TPG] = clk; + /* la */ clk = tegra_clk_register_periph("la", la_parents, ARRAY_SIZE(la_parents), &tegra210_la, clk_base, -- 2.7.4