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Subject: Re: clk: Lantiq/Intel: XWAY CGU support
To:     Jorge Amoros-Argos <joramar76@gmail.com>,
        linux-kernel@vger.kernel.org
Cc:     john@phrozen.org, martin.blumenstingl@googlemail.com
References: <20200404105309.0000745d@gmail.com>
From:   Hauke Mehrtens <hauke@hauke-m.de>
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Message-ID: <743865de-c69c-836c-a74f-f50ccaaed9b3@hauke-m.de>
Date:   Wed, 15 Apr 2020 00:00:20 +0200
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On 4/4/20 10:53 AM, Jorge Amoros-Argos wrote:
> Dear community,
>=20
> This is addresed to the Lantiq/Intel developers for the SoC's VRX200 an=
d
> XWAY in general.
>=20
> I'm trying to port the current sources to the common clock framework fo=
r
> Openwrt.

Thanks for looking into this. this SoC should really be converted to the
common clock framework.


> For this purpose, I'd need to have a good knowledge of both clock
> providers and consumers in order to update the device tree and also the=

> drivers. This means hardware (how devices are connected) and software
> (what registers do what?)
>=20
> There's no such low level detail after all my investigations, which are=

> shown here:
>=20
>      https://github.com/Mandrake-Lee/Lantiq_XWAY_CGU
>=20
> For instance, the full structure of PLL2 register remains a mistery and=

> also its output; OCP selector, is a kind of divider?; PCIe generator is=

> located where? PMU, is just a gate controller or a provider itself?
>=20
> I'd really appreciate if you could share some details in order to start=

> the job.

A common clock framework driver for the Lightning Mountain(LGM) SoC is
currently being reviewed on the upstream mailling list:
https://lkml.org/lkml/2020/3/24/4
there could still be some similarities between the VRX200 and the LGM,
but there are some generations in between and with the xrx500 many
registers in the CGU block changed.

Martin started to write a driver some years ago:
https://github.com/xdarklight/linux/commits/lantiq-clk-20160620
But this does not really models the clock tree.

Be aware that the clock tree is not so simple, it has a lot of dividers.

Hauke


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