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Date:   Wed, 15 Apr 2020 07:50:09 +0200
From:   Oleksij Rempel <o.rempel@pengutronix.de>
To:     peng.fan@nxp.com
Cc:     shawnguo@kernel.org, s.hauer@pengutronix.de, robh+dt@kernel.org,
        jaswinder.singh@linaro.org, linux@rempel-privat.de,
        devicetree@vger.kernel.org, Anson.Huang@nxp.com,
        linux-kernel@vger.kernel.org, linux-imx@nxp.com,
        kernel@pengutronix.de, festevam@gmail.com,
        linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 2/2] arm64: dts: imx8qxp: support scu mailbox channel
Message-ID: <20200415055009.uxkzy4j3l24dvvyv@pengutronix.de>
References: <1586870668-32630-1-git-send-email-peng.fan@nxp.com>
 <1586870668-32630-2-git-send-email-peng.fan@nxp.com>
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On Tue, Apr 14, 2020 at 09:24:28PM +0800, peng.fan@nxp.com wrote:
> From: Peng Fan <peng.fan@nxp.com>
>=20
> With mailbox driver support i.MX8 SCU MU channel, we could
> use it to avoid trigger interrupts for each TR/RR registers
> in one MU, instead, only one RX interrupt for a recv and
> one TX interrupt for a send.
>=20
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>

> ---
>=20
> Note:
>  This patch needs https://patchwork.kernel.org/patch/11446659/
>  The other three patches in the patchset has been in linux-next
>=20
>  arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 18 ++++++------------
>  1 file changed, 6 insertions(+), 12 deletions(-)
>=20
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot=
/dts/freescale/imx8qxp.dtsi
> index e8ffb7590656..d1c3c98e4b39 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> @@ -141,17 +141,11 @@
> =20
>  	scu {
>  		compatible =3D "fsl,imx-scu";
> -		mbox-names =3D "tx0", "tx1", "tx2", "tx3",
> -			     "rx0", "rx1", "rx2", "rx3",
> +		mbox-names =3D "tx0",
> +			     "rx0",
>  			     "gip3";
>  		mboxes =3D <&lsio_mu1 0 0
> -			  &lsio_mu1 0 1
> -			  &lsio_mu1 0 2
> -			  &lsio_mu1 0 3
>  			  &lsio_mu1 1 0
> -			  &lsio_mu1 1 1
> -			  &lsio_mu1 1 2
> -			  &lsio_mu1 1 3
>  			  &lsio_mu1 3 3>;
> =20
>  		clk: clock-controller {
> @@ -548,14 +542,14 @@
>  		};
> =20
>  		lsio_mu1: mailbox@5d1c0000 {
> -			compatible =3D "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
> +			compatible =3D "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
>  			reg =3D <0x5d1c0000 0x10000>;
>  			interrupts =3D <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
>  			#mbox-cells =3D <2>;
>  		};
> =20
>  		lsio_mu2: mailbox@5d1d0000 {
> -			compatible =3D "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
> +			compatible =3D "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
>  			reg =3D <0x5d1d0000 0x10000>;
>  			interrupts =3D <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
>  			#mbox-cells =3D <2>;
> @@ -563,7 +557,7 @@
>  		};
> =20
>  		lsio_mu3: mailbox@5d1e0000 {
> -			compatible =3D "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
> +			compatible =3D "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
>  			reg =3D <0x5d1e0000 0x10000>;
>  			interrupts =3D <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
>  			#mbox-cells =3D <2>;
> @@ -571,7 +565,7 @@
>  		};
> =20
>  		lsio_mu4: mailbox@5d1f0000 {
> -			compatible =3D "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
> +			compatible =3D "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
>  			reg =3D <0x5d1f0000 0x10000>;
>  			interrupts =3D <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
>  			#mbox-cells =3D <2>;
> --=20
> 2.16.4
>=20
>=20
>=20

--=20
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