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From:   Daniel Vetter <daniel@ffwll.ch>
Date:   Wed, 15 Apr 2020 11:16:01 +0200
Message-ID: <CAKMK7uEYUnX3p0QUtosOaiB_9Z8epFkc8HxtBDW=mCTUrziPxw@mail.gmail.com>
Subject: Re: [PATCH] Optimized division operation to shift operation
To:     =?UTF-8?Q?Christian_K=C3=B6nig?= <christian.koenig@amd.com>
Cc:     Jani Nikula <jani.nikula@linux.intel.com>,
        Alex Deucher <alexdeucher@gmail.com>,
        Bernard Zhao <bernard@vivo.com>,
        Alex Sierra <alex.sierra@amd.com>,
        David Airlie <airlied@linux.ie>, Oak Zeng <Oak.Zeng@amd.com>,
        LKML <linux-kernel@vger.kernel.org>,
        Maling list - DRI developers 
        <dri-devel@lists.freedesktop.org>, kernel@vivo.com,
        Huang Rui <ray.huang@amd.com>,
        amd-gfx list <amd-gfx@lists.freedesktop.org>,
        Alex Deucher <alexander.deucher@amd.com>,
        Xiaojie Yuan <xiaojie.yuan@amd.com>,
        Sam Ravnborg <sam@ravnborg.org>,
        Felix Kuehling <Felix.Kuehling@amd.com>,
        Kent Russell <kent.russell@amd.com>
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On Wed, Apr 15, 2020 at 9:57 AM Christian K=C3=B6nig
<christian.koenig@amd.com> wrote:
>
> Am 15.04.20 um 09:41 schrieb Jani Nikula:
> > On Tue, 14 Apr 2020, Alex Deucher <alexdeucher@gmail.com> wrote:
> >> On Tue, Apr 14, 2020 at 9:05 AM Bernard Zhao <bernard@vivo.com> wrote:
> >>> On some processors, the / operate will call the compiler`s div lib,
> >>> which is low efficient, We can replace the / operation with shift,
> >>> so that we can replace the call of the division library with one
> >>> shift assembly instruction.
> > This was applied already, and it's not in a driver I look after... but
> > to me this feels like something that really should be
> > justified. Using >> instead of / for multiples of 2 division mattered 2=
0
> > years ago, I'd be surprised if it still did on modern compilers.
>
> I have similar worries, especially since we replace the "/ (4 * 2)" with
> ">> 3" it's making the code just a bit less readable.
>
> And that the code runs exactly once while loading the driver and pushing
> the firmware into the hardware. So performance is completely irrelevant
> here.

Yeah, and even in general I'd really want to see proof that such bad
compilers exist first. Doing a peephole pass for stuff like this is
like undergrad compiler course stuff. Also I'd trust the compiler's
call on which is faster much more than humans doing a manual peephole
pass.

Or am I just massively biased from all the layman following of what
kind of our gl/vk/compute compiler people are doing on a daily basis?
-Daniel

>
> Regards,
> Christian.
>
> >
> > BR,
> > Jani.
> >
> >
> >>> Signed-off-by: Bernard Zhao <bernard@vivo.com>
> >> Applied.  thanks.
> >>
> >> Alex
> >>
> >>> ---
> >>>   drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 4 ++--
> >>>   drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 4 ++--
> >>>   drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 4 ++--
> >>>   3 files changed, 6 insertions(+), 6 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/=
amd/amdgpu/gmc_v6_0.c
> >>> index b205039..66cd078 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> >>> @@ -175,10 +175,10 @@ static int gmc_v6_0_mc_load_microcode(struct am=
dgpu_device *adev)
> >>>          amdgpu_ucode_print_mc_hdr(&hdr->header);
> >>>
> >>>          adev->gmc.fw_version =3D le32_to_cpu(hdr->header.ucode_versi=
on);
> >>> -       regs_size =3D le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2)=
;
> >>> +       regs_size =3D le32_to_cpu(hdr->io_debug_size_bytes) >> 3;
> >>>          new_io_mc_regs =3D (const __le32 *)
> >>>                  (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_arra=
y_offset_bytes));
> >>> -       ucode_size =3D le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
> >>> +       ucode_size =3D le32_to_cpu(hdr->header.ucode_size_bytes) >> 2=
;
> >>>          new_fw_data =3D (const __le32 *)
> >>>                  (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_=
array_offset_bytes));
> >>>
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/=
amd/amdgpu/gmc_v7_0.c
> >>> index 9da9596..ca26d63 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> >>> @@ -193,10 +193,10 @@ static int gmc_v7_0_mc_load_microcode(struct am=
dgpu_device *adev)
> >>>          amdgpu_ucode_print_mc_hdr(&hdr->header);
> >>>
> >>>          adev->gmc.fw_version =3D le32_to_cpu(hdr->header.ucode_versi=
on);
> >>> -       regs_size =3D le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2)=
;
> >>> +       regs_size =3D le32_to_cpu(hdr->io_debug_size_bytes) >> 3;
> >>>          io_mc_regs =3D (const __le32 *)
> >>>                  (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_arra=
y_offset_bytes));
> >>> -       ucode_size =3D le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
> >>> +       ucode_size =3D le32_to_cpu(hdr->header.ucode_size_bytes) >> 2=
;
> >>>          fw_data =3D (const __le32 *)
> >>>                  (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_=
array_offset_bytes));
> >>>
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/=
amd/amdgpu/gmc_v8_0.c
> >>> index 27d83204..295039c 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> >>> @@ -318,10 +318,10 @@ static int gmc_v8_0_tonga_mc_load_microcode(str=
uct amdgpu_device *adev)
> >>>          amdgpu_ucode_print_mc_hdr(&hdr->header);
> >>>
> >>>          adev->gmc.fw_version =3D le32_to_cpu(hdr->header.ucode_versi=
on);
> >>> -       regs_size =3D le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2)=
;
> >>> +       regs_size =3D le32_to_cpu(hdr->io_debug_size_bytes) >> 3;
> >>>          io_mc_regs =3D (const __le32 *)
> >>>                  (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_arra=
y_offset_bytes));
> >>> -       ucode_size =3D le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
> >>> +       ucode_size =3D le32_to_cpu(hdr->header.ucode_size_bytes) >> 2=
;
> >>>          fw_data =3D (const __le32 *)
> >>>                  (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_=
array_offset_bytes));
> >>>
> >>> --
> >>> 2.7.4
> >>>
> >>> _______________________________________________
> >>> amd-gfx mailing list
> >>> amd-gfx@lists.freedesktop.org
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> >> _______________________________________________
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>
> _______________________________________________
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> dri-devel@lists.freedesktop.org
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--=20
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch