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[23.128.96.18]) by mx.google.com with ESMTP id p26si8296090ejd.193.2020.04.15.16.50.04; Wed, 15 Apr 2020 16:50:27 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S369806AbgDOMfX (ORCPT + 99 others); Wed, 15 Apr 2020 08:35:23 -0400 Received: from m17618.mail.qiye.163.com ([59.111.176.18]:57149 "EHLO m17618.mail.qiye.163.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S369749AbgDOMeY (ORCPT ); Wed, 15 Apr 2020 08:34:24 -0400 Received: from ubuntu.localdomain (unknown [58.251.74.226]) by m17618.mail.qiye.163.com (Hmail) with ESMTPA id 26B094E207B; Wed, 15 Apr 2020 20:34:21 +0800 (CST) From: Wang Wenhu To: gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, oss@buserror.net, christophe.leroy@c-s.fr, linuxppc-dev@lists.ozlabs.org Cc: kernel@vivo.com, Wang Wenhu , Michael Ellerman Subject: [PATCH 1/5] powerpc: 85xx: make FSL_85XX_CACHE_SRAM configurable Date: Wed, 15 Apr 2020 05:33:42 -0700 Message-Id: <20200415123346.116212-2-wenhu.wang@vivo.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200415123346.116212-1-wenhu.wang@vivo.com> References: <20200415123346.116212-1-wenhu.wang@vivo.com> X-HM-Spam-Status: e1kfGhgUHx5ZQUtXWQgYFAkeWUFZSFVMQk5LS0tLTE1JQkhCTllXWShZQU hPN1dZLVlBSVdZCQ4XHghZQVk1NCk2OjckKS43PlkG X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6PQg6Nxw*PDg8Qwg6KU0TIzAQ Dh8aCy9VSlVKTkNNQk5PS01KTkhIVTMWGhIXVQweFRMOVQwaFRw7DRINFFUYFBZFWVdZEgtZQVlO Q1VJTkpVTE9VSUlNWVdZCAFZQUlCSk83Bg++ X-HM-Tid: 0a717dd5466a9376kuws26b094e207b Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Enable FSL_85XX_CACHE_SRAM selection. On e500 platforms, the cache could be configured and used as a piece of SRAM which is hignly friendly for some user level application performances. Cc: Greg Kroah-Hartman Cc: Christophe Leroy Cc: Scott Wood Cc: Michael Ellerman Cc: linuxppc-dev@lists.ozlabs.org Signed-off-by: Wang Wenhu --- arch/powerpc/platforms/85xx/Kconfig | 2 +- arch/powerpc/platforms/Kconfig.cputype | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig index fa3d29dcb57e..6debb4f1b9cc 100644 --- a/arch/powerpc/platforms/85xx/Kconfig +++ b/arch/powerpc/platforms/85xx/Kconfig @@ -17,7 +17,7 @@ if FSL_SOC_BOOKE if PPC32 config FSL_85XX_CACHE_SRAM - bool + bool "Freescale 85xx Cache-Sram" select PPC_LIB_RHEAP help When selected, this option enables cache-sram support diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype index 0c3c1902135c..1921e9a573e8 100644 --- a/arch/powerpc/platforms/Kconfig.cputype +++ b/arch/powerpc/platforms/Kconfig.cputype @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 config PPC32 - bool + bool "32-bit kernel" default y if !PPC64 select KASAN_VMALLOC if KASAN && MODULES @@ -15,6 +15,7 @@ config PPC_BOOK3S_32 bool menu "Processor support" + choice prompt "Processor Type" depends on PPC32 @@ -211,9 +212,9 @@ config PPC_BOOK3E depends on PPC_BOOK3E_64 config E500 + bool "e500 Support" select FSL_EMB_PERFMON select PPC_FSL_BOOK3E - bool config PPC_E500MC bool "e500mc Support" -- 2.17.1