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From:   Rob Herring <robh@kernel.org>
Date:   Wed, 15 Apr 2020 08:54:04 -0500
Message-ID: <CAL_JsqLyEy_++q5+JsUmg=gpgh=xkSP7XiQrDvje7tiUHzB8KQ@mail.gmail.com>
Subject: Re: [PATCH 2/2] devicetree: bindings: phy: Document dwc3 qcom phy
To:     Ansuel Smith <ansuelsmth@gmail.com>
Cc:     Andy Gross <agross@kernel.org>,
        Bjorn Andersson <bjorn.andersson@linaro.org>,
        Kishon Vijay Abraham I <kishon@ti.com>,
        Mark Rutland <mark.rutland@arm.com>,
        linux-arm-msm <linux-arm-msm@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        devicetree@vger.kernel.org
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On Wed, Apr 15, 2020 at 7:26 AM <ansuelsmth@gmail.com> wrote:
>
> > On Fri, Apr 03, 2020 at 02:26:05AM +0200, Ansuel Smith wrote:
> > > Document dwc3 qcom phy hs and ss phy bindings needed to correctly
> > > inizialize and use usb on ipq806x SoC
> > >
> > > Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> > > ---
> > >  .../bindings/phy/qcom,dwc3-hs-usb-phy.yaml    | 65
> > +++++++++++++++++++
> > >  .../bindings/phy/qcom,dwc3-ss-usb-phy.yaml    | 65
> > +++++++++++++++++++
> > >  2 files changed, 130 insertions(+)
> > >  create mode 100644
> > Documentation/devicetree/bindings/phy/qcom,dwc3-hs-usb-phy.yaml
> > >  create mode 100644
> > Documentation/devicetree/bindings/phy/qcom,dwc3-ss-usb-phy.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/phy/qcom,dwc3-hs-usb-
> > phy.yaml b/Documentation/devicetree/bindings/phy/qcom,dwc3-hs-usb-
> > phy.yaml
> > > new file mode 100644
> > > index 000000000000..0bb59e3c2ab8
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/phy/qcom,dwc3-hs-usb-
> > phy.yaml
> > > @@ -0,0 +1,65 @@
> > > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/phy/qcom,dwc3-hs-usb-phy.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: Qualcomm DWC3 HS PHY CONTROLLER
> > > +
> > > +maintainers:
> > > +  - Ansuel Smith <ansuelsmth@gmail.com>
> > > +
> > > +description:
> > > +  DWC3 PHY nodes are defined to describe on-chip Synopsis Physical
> > layer
> > > +  controllers. Each DWC3 PHY controller should have its own node.
> > > +
> > > +properties:
> > > +  compatible:
> > > +    const: qcom,dwc3-hs-usb-phy
> > > +
> > > +  "#phy-cells":
> > > +    const: 0
> > > +
> > > +  regmap:
> > > +    maxItems: 1
> > > +    description: phandle to usb3 dts definition
> > > +
> > > +  clocks:
> > > +    minItems: 1
> > > +    maxItems: 2
> > > +
> > > +  clock-names:
> > > +    minItems: 1
> > > +    maxItems: 2
> > > +    description: |
> > > +      - "ref" Is required
> > > +      - "xo"       Optional external reference clock
> > > +    items:
> > > +      - const: ref
> > > +      - const: xo
> > > +
> > > +required:
> > > +  - compatible
> > > +  - "#phy-cells"
> > > +  - regmap
> > > +  - clocks
> > > +  - clock-names
> > > +
> > > +examples:
> > > +  - |
> > > +    #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
> > > +
> > > +    hs_phy_0: hs_phy_0 {
> > > +      compatible = "qcom,dwc3-hs-usb-phy";
> > > +      regmap = <&usb3_0>;
> >
> > If the registers for the phy are part of 'qcom,dwc3' then make this node
> > a child of it.
> >
>
> Making this node a child of qcom,dwc3 cause malfunction of the driver.

Fix the driver then.

Rob