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Cc:     devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-pci@vger.kernel.org
Subject: [PATCH 3/8] PCI: aardvark: Start link training immediately after enabling link training
Date:   Wed, 15 Apr 2020 18:00:49 +0200
Message-Id: <20200415160054.951-4-pali@kernel.org>
In-Reply-To: <20200415160054.951-1-pali@kernel.org>
References: <20200415160054.951-1-pali@kernel.org>
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Sender: linux-kernel-owner@vger.kernel.org
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Adding even 100ms (PCI_PM_D3COLD_WAIT) delay between enabling link training
and starting link training cause that some Compex WLE900VX cards are not
detected.

So move code for enabling link training after PCI_PM_D3COLD_WAIT delay.

This change fixes Compex WLE900VX cards detection on Turris MOX after cold
boot.

Fixes: f4c7d053d7f7 ("PCI: aardvark: Wait for endpoint to be ready before
training link")

Signed-off-by: Pali Rohár <pali@kernel.org>
---
 drivers/pci/controller/pci-aardvark.c | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
index ad4f0fa57624..756b31c4d20b 100644
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -322,11 +322,6 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
 	reg |= LANE_COUNT_1;
 	advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
 
-	/* Enable link training */
-	reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
-	reg |= LINK_TRAINING_EN;
-	advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
-
 	/* Enable MSI */
 	reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
 	reg |= PCIE_CORE_CTRL2_MSI_ENABLE;
@@ -368,6 +363,16 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
 	 */
 	msleep(PCI_PM_D3COLD_WAIT);
 
+	/*
+	 * Do "Enable link training" and "Start link training" in a row without
+	 * any delay between them. Adding even 100ms delay (PCI_PM_D3COLD_WAIT)
+	 * cause that some Compex WLE900VX cards are not detected.
+	 */
+
+	/* Enable link training */
+	reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
+	reg |= LINK_TRAINING_EN;
+	advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
 	/* Start link training */
 	reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG);
 	reg |= PCIE_CORE_LINK_TRAINING;
-- 
2.20.1