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Subject: Re: [PATCH 1/7] mmc: sdhci: fix base clock usage in preset value
To:     =?UTF-8?B?TWljaGHFgiBNaXJvc8WCYXc=?= <mirq-linux@rere.qmqm.pl>
Cc:     Ulf Hansson <ulf.hansson@linaro.org>,
        Kevin Liu <kliu5@marvell.com>,
        Michal Simek <michal.simek@xilinx.com>,
        Suneel Garapati <suneel.garapati@xilinx.com>,
        linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org,
        Al Cooper <alcooperx@gmail.com>
References: <cover.1585827904.git.mirq-linux@rere.qmqm.pl>
 <23c3fe72b0ff0eabdbf3a45023a76da1b18a7e90.1585827904.git.mirq-linux@rere.qmqm.pl>
 <218dd61b-48cc-a161-240f-b3823e8f48cb@intel.com>
 <20200415162839.GD19897@qmqm.qmqm.pl>
From:   Adrian Hunter <adrian.hunter@intel.com>
Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki,
 Business Identity Code: 0357606 - 4, Domiciled in Helsinki
Message-ID: <57b494b8-cae9-df10-2a4d-db02e7212f23@intel.com>
Date:   Thu, 16 Apr 2020 11:26:41 +0300
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On 15/04/20 7:28 pm, Micha? Miros?aw wrote:
> On Wed, Apr 15, 2020 at 03:25:52PM +0300, Adrian Hunter wrote:
>> On 2/04/20 2:54 pm, Micha? Miros?aw wrote:
>>> Fixed commit added an unnecessary read of CLOCK_CONTROL. The value read
>>> is overwritten for programmable clock preset, but is carried over for
>>> divided clock preset. This can confuse sdhci_enable_clk() if the register
>>> has enable bits set for some reason at time time of clock calculation.
>>> value to be ORed with enable flags. Remove the read.
>>
>> The read is not needed, but drivers usually manage the enable bits,
>> especially disabling the clock before changing the frequency.  What driver
>> is it?
> 
> Hopefully no driver requires this. It's just removing a trap.

The only driver that looks like it would benefit is sdhci-brcmstb because it
does not clear enable bits in sdhci_brcmstb_set_clock().  Adding Al Cooper.
Al, can you ack this?