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Subject: Re: [PATCH v1 2/2] mtd: rawnand: Add NAND controller support on Intel
 LGM SoC
To:     Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc:     anders.roxell@linaro.org, andriy.shevchenko@intel.com,
        arnd@arndb.de, boris.brezillon@collabora.com,
        brendanhiggins@google.com, cheol.yong.kim@intel.com,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-mtd@lists.infradead.org, masonccyang@mxic.com.tw,
        miquel.raynal@bootlin.com, piotrs@cadence.com,
        qi-ming.wu@intel.com, richard@nod.at, robh+dt@kernel.org,
        tglx@linutronix.de, vigneshr@ti.com
References: <20200414022433.36622-3-vadivel.muruganx.ramuthevar@linux.intel.com>
 <20200415220533.733834-1-martin.blumenstingl@googlemail.com>
From:   "Ramuthevar, Vadivel MuruganX" 
        <vadivel.muruganx.ramuthevar@linux.intel.com>
Message-ID: <c33c8653-16a2-5bcd-97a9-511d958b755a@linux.intel.com>
Date:   Thu, 16 Apr 2020 17:35:26 +0800
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Hi Martin,

     Thank you so much for review comments and your time...

On 16/4/2020 6:05 am, Martin Blumenstingl wrote:
> Hi,
>
> first of all: thank you for working on upstreaming this.
> Especially since you are going to use the new exec_op style in v2 as
> Boris suggested.
>
>> From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
>>
>> This patch adds the new IP of Nand Flash Controller(NFC) support
>> on Intel's Lightning Mountain(LGM) SoC.
>>
>> DMA is used for burst data transfer operation, also DMA HW supports
>> aligned 32bit memory address and aligned data access by default.
>> DMA burst of 8 supported. Data register used to support the read/write
>> operation from/to device.
> I am wondering how this new hardware is different from the Lantiq NAND
> controller IP - for which there is already a driver in mainline (it's
> in drivers/mtd/nand/raw/xway_nand.c).
> The CON and WAIT registers look suspiciously similar.
>
> As far as I understand the "old" SoCs (VRX200 and earlier) don't have
> a built-in ECC engine. This seems to have changed with ARX300 though
> (again, AFAIK).
>
> A bit of lineage on these SoCs (initially these were developed by
> Infineon. Lantiq then started as an Infineon spin-off in 2009 and
> was then acquired by Intel in 2015):
> - Danube
> - ARX100 from 2008/2009
> - VRX200 from 2009/2010
> - ARX300 from 2014
> - GRX350 from 2015/2016
> - GRX550 from 2017
> - and now finally: LGM from 2020 (est.)
>
> The existing xway_nand driver supports the Danube, ARX100 and VRX200
> SoCs.
Lantiq upstreamed a driver for an older version of this IP core 8 years 
ago, see here:
https://elixir.bootlin.com/linux/v5.5.6/source/drivers/mtd/nand/raw/xway_nand.c 
It does not support DMA and ECC.
This upstream driver works with the xrx200, I do not know how well it 
works with other SoCs.

Regards
Vadivel
>
>
> Best regards,
> Martin