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[23.128.96.18]) by mx.google.com with ESMTP id b26si7902551edr.228.2020.04.16.08.44.49; Thu, 16 Apr 2020 08:45:13 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2635437AbgDPPmI (ORCPT + 99 others); Thu, 16 Apr 2020 11:42:08 -0400 Received: from mail-ot1-f67.google.com ([209.85.210.67]:35019 "EHLO mail-ot1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2395513AbgDPPl7 (ORCPT ); Thu, 16 Apr 2020 11:41:59 -0400 Received: by mail-ot1-f67.google.com with SMTP id e20so3455780otl.2; Thu, 16 Apr 2020 08:41:59 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=v2r2r7O0CFpemVMZF52M89j+FDaTZj9iicBxWLrdGKQ=; b=cWxSd2WFCpFpPKJYhn5g9auh747t7vpQLWrKQiFns9euE2mwmJAxx4OswvcW1SJdNr 5pBjf6DV7dvZCsq/fSzoUVXlvHRMkSx5+4PlPcqxb8BQm35ojCCp0MlczkoZdT58Ta9L BLYBbqLol5UHyDawboY8p67ytB3sBdgT3UQNQYdCNc4vftu64uKewgavnd19LZdU6PWA R96S9mVXSX/WFaMjCeyPrONJ43dwpqq0/TAWr1f9VwP6OVDa3Bqix21AjhDx+GCjR7ck uKHyl+TEPCjWd8upAIVIeBD/5m6jvkVL9UlByAYK3e+k1npepC+Ytb0Vcxb/mHfkUayd wrNg== X-Gm-Message-State: AGi0PuYG8NhUrTEKoXVwKRBu6oI4hiyibXJJem/CiN5kOx3pT3FFcZ1v l18MSUDnR7YzSGa3yYkHEEWvNbNvbGQtpZ1Q3RU= X-Received: by 2002:a9d:6ac8:: with SMTP id m8mr17036281otq.262.1587051718557; Thu, 16 Apr 2020 08:41:58 -0700 (PDT) MIME-Version: 1.0 References: <20200416054745.740-1-ggherdovich@suse.cz> <20200416054745.740-2-ggherdovich@suse.cz> In-Reply-To: <20200416054745.740-2-ggherdovich@suse.cz> From: "Rafael J. Wysocki" Date: Thu, 16 Apr 2020 17:41:47 +0200 Message-ID: Subject: Re: [PATCH 1/4] x86, sched: Bail out of frequency invariance if base frequency is unknown To: Giovanni Gherdovich Cc: Srinivas Pandruvada , Thomas Gleixner , Ingo Molnar , Peter Zijlstra , Borislav Petkov , Len Brown , "Rafael J . Wysocki" , "the arch/x86 maintainers" , Linux PM , Linux Kernel Mailing List , Mel Gorman , Doug Smythies , Like Xu , Neil Rickert , Chris Wilson Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Apr 16, 2020 at 7:48 AM Giovanni Gherdovich wrote: > > Some hypervisors such as VMWare ESXi 5.5 advertise support for > X86_FEATURE_APERFMPERF but then fill all MSR's with zeroes. In particular, > MSR_PLATFORM_INFO set to zero tricks the code that wants to know the base > clock frequency of the CPU (highest non-turbo frequency), producing a > division by zero when computing the ratio turbo_freq/base_freq necessary > for frequency invariant accounting. > > It is to be noted that even if MSR_PLATFORM_INFO contained the appropriate > data, APERF and MPERF are constantly zero on ESXi 5.5, thus freq-invariance > couldn't be done in principle (not that it would make a lot of sense in a > VM anyway). The real problem is advertising X86_FEATURE_APERFMPERF. This > appears to be fixed in more recent versions: ESXi 6.7 doesn't advertise > that feature. > > Signed-off-by: Giovanni Gherdovich > Fixes: 1567c3e3467c ("x86, sched: Add support for frequency invariance") Please feel free to add Acked-by: Rafael J. Wysocki to all patches in the series and I'm expecting them to be routed through tip. Thanks! > --- > arch/x86/kernel/smpboot.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c > index fe3ab9632f3b..3a318ec9bc17 100644 > --- a/arch/x86/kernel/smpboot.c > +++ b/arch/x86/kernel/smpboot.c > @@ -1985,6 +1985,15 @@ static bool intel_set_max_freq_ratio(void) > return false; > > out: > + /* > + * Some hypervisors advertise X86_FEATURE_APERFMPERF > + * but then fill all MSR's with zeroes. > + */ > + if (!base_freq) { > + pr_debug("Couldn't determine cpu base frequency, necessary for scale-invariant accounting.\n"); > + return false; > + } > + > arch_turbo_freq_ratio = div_u64(turbo_freq * SCHED_CAPACITY_SCALE, > base_freq); > arch_set_max_freq_ratio(turbo_disabled()); > -- > 2.16.4 >