Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
MIME-Version: 1.0
References: <cover.1585827904.git.mirq-linux@rere.qmqm.pl> <23c3fe72b0ff0eabdbf3a45023a76da1b18a7e90.1585827904.git.mirq-linux@rere.qmqm.pl>
 <218dd61b-48cc-a161-240f-b3823e8f48cb@intel.com> <20200415162839.GD19897@qmqm.qmqm.pl>
 <57b494b8-cae9-df10-2a4d-db02e7212f23@intel.com>
In-Reply-To: <57b494b8-cae9-df10-2a4d-db02e7212f23@intel.com>
From:   Alan Cooper <alcooperx@gmail.com>
Date:   Fri, 17 Apr 2020 09:55:19 -0400
Message-ID: <CAOGqxeVB2FTTi4DFynVj4hc+EcagMCg1j8F29L+9zRt1DKfbBQ@mail.gmail.com>
Subject: Re: [PATCH 1/7] mmc: sdhci: fix base clock usage in preset value
To:     Adrian Hunter <adrian.hunter@intel.com>
Cc:     =?UTF-8?B?TWljaGHFgiBNaXJvc8WCYXc=?= <mirq-linux@rere.qmqm.pl>,
        Ulf Hansson <ulf.hansson@linaro.org>,
        Kevin Liu <kliu5@marvell.com>,
        Michal Simek <michal.simek@xilinx.com>,
        Suneel Garapati <suneel.garapati@xilinx.com>,
        linux-mmc <linux-mmc@vger.kernel.org>,
        ": Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk

Acked-by: Al Cooper <alcooperx@gmail.com>On Thu, Apr 16, 2020 at 4:27
AM Adrian Hunter <adrian.hunter@intel.com> wrote:
>
> On 15/04/20 7:28 pm, Micha=C5=82 Miros=C5=82aw wrote:
> > On Wed, Apr 15, 2020 at 03:25:52PM +0300, Adrian Hunter wrote:
> >> On 2/04/20 2:54 pm, Micha=C5=82 Miros=C5=82aw wrote:
> >>> Fixed commit added an unnecessary read of CLOCK_CONTROL. The value re=
ad
> >>> is overwritten for programmable clock preset, but is carried over for
> >>> divided clock preset. This can confuse sdhci_enable_clk() if the regi=
ster
> >>> has enable bits set for some reason at time time of clock calculation=
.
> >>> value to be ORed with enable flags. Remove the read.
> >>
> >> The read is not needed, but drivers usually manage the enable bits,
> >> especially disabling the clock before changing the frequency.  What dr=
iver
> >> is it?
> >
> > Hopefully no driver requires this. It's just removing a trap.
>
> The only driver that looks like it would benefit is sdhci-brcmstb because=
 it
> does not clear enable bits in sdhci_brcmstb_set_clock().  Adding Al Coope=
r.
> Al, can you ack this?

sdhci_brcmstb_set_clock() assumed that sdhci_calc_clk() would always
return the divider value without the enable set, so this fixes a case
for DDR52 where the enable was not being cleared when the divider
value was changed.
Acked-by: Al Cooper <alcooperx@gmail.com>