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From:   Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Date:   Fri, 17 Apr 2020 20:58:04 +0200
Message-ID: <CAFBinCCUM1Ht1_yRcbG=exJBign=YBX1+xUr8kz=3pJy2PxsnQ@mail.gmail.com>
Subject: Re: [PATCH v3 2/8] usb: dwc3: meson-g12a: support the GXL/GXM DWC3
 host phy disconnect
To:     Neil Armstrong <narmstrong@baylibre.com>
Cc:     kishon@ti.com, balbi@kernel.org, khilman@baylibre.com,
        linux-amlogic@lists.infradead.org, linux-usb@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
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On Thu, Apr 16, 2020 at 2:19 PM Neil Armstrong <narmstrong@baylibre.com> wrote:
>
> On the Amlogic GXL/GXM SoCs, the OTG PHY status signals are always
> connected to the DWC3 controller, thus crashing the controller when
> switching to OTG mode when port is not populated with a device/cable to
> Host.
>
> Amlogic added a bit to disconnect the OTG PHY status signals from the DWC3
> to be used when switching the OTG PHY as Device to the DWC2 controller.
>
> The drawback is that it makes the DWC3 port state machine stall and needs
> a full reset of the DWC3 controller to get connect status to the port
> connected to the OTG PHY, but not the other one.
>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
one nit-pick below. apart from that:
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

[...]
>         if (mode == PHY_MODE_USB_DEVICE) {
> +               if (priv->otg_mode != USB_DR_MODE_OTG &&
> +                   priv->drvdata->otg_phy_host_port_disable)
> +                       /* Isolate the OTG PHY port from the Host Controller */
> +                       regmap_update_bits(priv->usb_glue_regmap, USB_R1,
> +                               USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK,
> +                               FIELD_PREP(USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK,
> +                                          BIT(USB2_OTG_PHY)));
if you have to re-send for whatever reason then I would like an empty
line here to make the code easier to read

>                 regmap_update_bits(priv->usb_glue_regmap, USB_R0,
>                                 USB_R0_U2D_ACT, USB_R0_U2D_ACT);
>                 regmap_update_bits(priv->usb_glue_regmap, USB_R0,
> @@ -297,6 +318,12 @@ static void dwc3_meson_g12a_usb_otg_apply_mode(struct dwc3_meson_g12a *priv,
>                 regmap_update_bits(priv->usb_glue_regmap, USB_R4,
>                                 USB_R4_P21_SLEEP_M0, USB_R4_P21_SLEEP_M0);
>         } else {
> +               if (priv->otg_mode != USB_DR_MODE_OTG &&
> +                   priv->drvdata->otg_phy_host_port_disable) {
> +                       regmap_update_bits(priv->usb_glue_regmap, USB_R1,
> +                               USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK, 0);
> +                       msleep(500);
> +               }
same as above - if you have to re-send for whatever reason then please
add an empty line here