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[23.128.96.18]) by mx.google.com with ESMTP id u24si8555948edb.250.2020.04.19.22.33.09; Sun, 19 Apr 2020 22:33:32 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725991AbgDTFcP (ORCPT + 99 others); Mon, 20 Apr 2020 01:32:15 -0400 Received: from mga12.intel.com ([192.55.52.136]:12657 "EHLO mga12.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725710AbgDTFcP (ORCPT ); Mon, 20 Apr 2020 01:32:15 -0400 IronPort-SDR: 6oyG2vKMOa0hTPyhx6mXHdG2FcqrGseStmRlPsCefKQyFBnnufZuAGktZOfGg2794v7FRvVAPa JPUCTw9UjV5Q== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Apr 2020 22:32:14 -0700 IronPort-SDR: 7fDoYv9l9Nuy27x9AnxUCje9cd2+eP2LwqC5xaYbuGbM+HfhdtRo1YsWes/ZNbby+iL8aYNbQy qEDy1uX+gCGQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,405,1580803200"; d="scan'208";a="288382574" Received: from ahunter-desktop.fi.intel.com (HELO [10.237.72.87]) ([10.237.72.87]) by orsmga008.jf.intel.com with ESMTP; 19 Apr 2020 22:32:12 -0700 Subject: Re: [PATCH 1/7] mmc: sdhci: fix base clock usage in preset value To: Alan Cooper Cc: =?UTF-8?B?TWljaGHFgiBNaXJvc8WCYXc=?= , Ulf Hansson , Kevin Liu , Michal Simek , Suneel Garapati , linux-mmc , ": Linux Kernel Mailing List" References: <23c3fe72b0ff0eabdbf3a45023a76da1b18a7e90.1585827904.git.mirq-linux@rere.qmqm.pl> <218dd61b-48cc-a161-240f-b3823e8f48cb@intel.com> <20200415162839.GD19897@qmqm.qmqm.pl> <57b494b8-cae9-df10-2a4d-db02e7212f23@intel.com> From: Adrian Hunter Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Message-ID: Date: Mon, 20 Apr 2020 08:31:20 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 17/04/20 4:55 pm, Alan Cooper wrote: > Acked-by: Al Cooper On Thu, Apr 16, 2020 at 4:27 > AM Adrian Hunter wrote: >> >> On 15/04/20 7:28 pm, Michał Mirosław wrote: >>> On Wed, Apr 15, 2020 at 03:25:52PM +0300, Adrian Hunter wrote: >>>> On 2/04/20 2:54 pm, Michał Mirosław wrote: >>>>> Fixed commit added an unnecessary read of CLOCK_CONTROL. The value read >>>>> is overwritten for programmable clock preset, but is carried over for >>>>> divided clock preset. This can confuse sdhci_enable_clk() if the register >>>>> has enable bits set for some reason at time time of clock calculation. >>>>> value to be ORed with enable flags. Remove the read. >>>> >>>> The read is not needed, but drivers usually manage the enable bits, >>>> especially disabling the clock before changing the frequency. What driver >>>> is it? >>> >>> Hopefully no driver requires this. It's just removing a trap. >> >> The only driver that looks like it would benefit is sdhci-brcmstb because it >> does not clear enable bits in sdhci_brcmstb_set_clock(). Adding Al Cooper. >> Al, can you ack this? > > sdhci_brcmstb_set_clock() assumed that sdhci_calc_clk() would always > return the divider value without the enable set, so this fixes a case > for DDR52 where the enable was not being cleared when the divider > value was changed. > Acked-by: Al Cooper > That is good to know. The commit message needs to be updated with that information, otherwise: Acked-by: Adrian Hunter