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charset="us-ascii" Content-ID: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 0a1e47db-3ea7-4456-9c8e-08d7e541ec79 X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Apr 2020 15:45:59.7853 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Qb7OpoJykMzv08Ugjdi5wpA3XwztgoOnUVswVWue+i2pRvkIpE+XfyTj+2JATTSVH167HRg7cZ8HDVBckcCR8E41XLJyIRIUfdqwc+N00AA= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR11MB4194 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Daniel, On Friday, April 17, 2020 8:46:19 PM EEST Daniel Walker wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know th= e > content is safe >=20 > The n25q256a supports 4-byte opcodes so lets add the flag. This is not true for all the n25q256a flashes. SPINOR_OP_PP_4B,=20 SPINOR_OP_BE_4K_4B and SPINOR_OP_SE_4B are valid just for the part numbers= =20 N25Q256A83ESF40x, N25Q256A83E1240x, and N25Q256A83ESFA0F. You need to differentiate between the aforementioned flashes and the rest i= n=20 the n25q256a, in order to add the 4-byte opcodes flag. Cheers, ta > Tested on Cisco IoT platform hardware using Marvell A7040 SoC. >=20 > This patch was base on one from Guo Yi . >=20 > Cc: xe-linux-external@cisco.com > Signed-off-by: Daniel Walker > --- > drivers/mtd/spi-nor/micron-st.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >=20 > diff --git a/drivers/mtd/spi-nor/micron-st.c > b/drivers/mtd/spi-nor/micron-st.c index 6c034b9718e2..471fe2bc2ba4 100644 > --- a/drivers/mtd/spi-nor/micron-st.c > +++ b/drivers/mtd/spi-nor/micron-st.c > @@ -37,7 +37,7 @@ static const struct flash_info st_parts[] =3D { > SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, > { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | > USE_FSR | SPI_NOR_DUAL_READ | > - SPI_NOR_QUAD_READ) }, > + SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, > { "mt25qu256a", INFO6(0x20bb19, 0x104400, 64 * 1024, 512, > SECT_4K | USE_FSR | SPI_NOR_DUAL_READ | > SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, > -- > 2.17.1