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Mon, 20 Apr 2020 16:25:51 +0000 From: "Daniel Walker (danielwa)" To: "Tudor.Ambarus@microchip.com" CC: "xe-linux-external(mailer list)" , "miquel.raynal@bootlin.com" , "richard@nod.at" , "vigneshr@ti.com" , "linux-mtd@lists.infradead.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH] mtd: spi-nor: Add 4B_OPCODES flag to n25q256a Thread-Topic: [PATCH] mtd: spi-nor: Add 4B_OPCODES flag to n25q256a Thread-Index: AQHWFzBbbqQ06SrDG0Ov1Hkds10F6g== Date: Mon, 20 Apr 2020 16:25:51 +0000 Message-ID: <20200420162550.GZ24466@zorba> References: <20200417174620.16420-1-danielwa@cisco.com> <12178429.kzmL6e4XO6@192.168.0.120> In-Reply-To: <12178429.kzmL6e4XO6@192.168.0.120> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-Auto-Response-Suppress: DR, OOF, AutoReply X-MS-TNEF-Correlator: user-agent: Mutt/1.9.4 (2018-02-28) authentication-results: spf=none (sender IP is ) smtp.mailfrom=danielwa@cisco.com; x-originating-ip: [128.107.241.173] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 54016b60-8d74-4013-feb6-08d7e5477ded x-ms-traffictypediagnostic: BYAPR11MB3336: x-ld-processed: 5ae1af62-9505-4097-a69a-c1553ef7840e,ExtAddr x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:6790; 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charset="us-ascii" Content-ID: <79F3F390E17E4B4A8410F2424536F794@namprd11.prod.outlook.com> Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 54016b60-8d74-4013-feb6-08d7e5477ded X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Apr 2020 16:25:51.3383 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 5ae1af62-9505-4097-a69a-c1553ef7840e X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: aMIKVq8LPthx6ADaNF2d369iCX9VMq2MiQQMGdKJKmzojZp+zCQzTTL5xeAd/ZY+20GO11OrD/2gjs5jYHgo3A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR11MB3336 X-OriginatorOrg: cisco.com X-Outbound-SMTP-Client: 173.36.7.13, xch-aln-003.cisco.com X-Outbound-Node: rcdn-core-12.cisco.com Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Apr 20, 2020 at 03:45:59PM +0000, Tudor.Ambarus@microchip.com wrote= : > Hi, Daniel, >=20 > On Friday, April 17, 2020 8:46:19 PM EEST Daniel Walker wrote: > > EXTERNAL EMAIL: Do not click links or open attachments unless you know = the > > content is safe > >=20 > > The n25q256a supports 4-byte opcodes so lets add the flag. >=20 > This is not true for all the n25q256a flashes. SPINOR_OP_PP_4B,=20 > SPINOR_OP_BE_4K_4B and SPINOR_OP_SE_4B are valid just for the part number= s=20 > N25Q256A83ESF40x, N25Q256A83E1240x, and N25Q256A83ESFA0F. >=20 > You need to differentiate between the aforementioned flashes and the rest= in=20 > the n25q256a, in order to add the 4-byte opcodes flag. How do you suggest I do that ? Can I add a new entry into this table with m= ore specific information about the chips ? Daniel=