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Nikolaus Schaller" , David Airlie , Daniel Vetter , Rob Herring , Mark Rutland , =?utf-8?Q?Beno=C3=AEt?= Cousson , Tony Lindgren , Paul Cercueil , Ralf Baechle , Paul Burton , James Hogan , Kukjin Kim , Krzysztof Kozlowski , Chen-Yu Tsai , Thomas Bogendoerfer , "open list:DRM PANEL DRIVERS" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Linux Kernel Mailing List , linux-omap , OpenPVRSGX Linux Driver Group , Discussions about the Letux Kernel , kernel@pyra-handheld.com, linux-mips@vger.kernel.org, arm-soc , linux-samsung-soc@vger.kernel.org Subject: Re: [PATCH v6 00/12] ARM/MIPS: DTS: add child nodes describing the PVRSGX GPU present in some OMAP SoC and JZ4780 (and many more) Message-ID: <20200421112129.zjmkmzo3aftksgka@gilmour.lan> References: <20200415101008.zxzxca2vlfsefpdv@gilmour.lan> <2E3401F1-A106-4396-8FE6-51CAB72926A4@goldelico.com> <20200415130233.rgn7xrtwqicptke2@gilmour.lan> <10969e64-fe1f-d692-4984-4ba916bd2161@gmail.com> <20200420073842.nx4xb3zqvu23arkc@gilmour.lan> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="bsmwn6lsujflbhcr" Content-Disposition: inline In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --bsmwn6lsujflbhcr Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi, On Tue, Apr 21, 2020 at 11:57:33AM +0200, Philipp Rossak wrote: > On 20.04.20 09:38, Maxime Ripard wrote: > > Hi, > >=20 > > On Fri, Apr 17, 2020 at 02:09:06PM +0200, Philipp Rossak wrote: > > > > > I'm a bit skeptical on that one since it doesn't even list the > > > > > interrupts connected to the GPU that the binding mandates. > > > >=20 > > > > I think he left it out for a future update. > > > > But best he comments himself. > > >=20 > > > I'm currently working on those bindings. They are now 90% done, but t= hey are > > > not finished till now. Currently there is some mainline support missi= ng to > > > add the full binding. The A83T and also the A31/A31s have a GPU Power= Off > > > Gating Register in the R_PRCM module, that is not supported right now= in > > > Mainline. The Register need to be written when the GPU is powered on = and > > > off. > > >=20 > > > @Maxime: I totally agree on your point that a demo needs to be provid= ed > > > before the related DTS patches should be provided. That's the reason = why I > > > added the gpu placeholder patches. > > > Do you have an idea how a driver for the R_PRCM stuff can look like? = I'm not > > > that experienced with the clock driver framework. > >=20 > > It looks like a power-domain to me, so you'd rather plug that into the = genpd > > framework. >=20 > I had a look on genpd and I'm not really sure if that fits. >=20 > It is basically some bit that verify that the clocks should be enabled or > disabled. No, it can do much more than that. It's a framework to control the SoCs pow= er domains, so clocks might be a part of it, but most of the time it's going t= o be about powering up a particular device. > I think this is better placed somewhere in the clocking framework. > I see there more similarities to the gating stuff. > Do you think it is suitable to implement it like the clock gating? I'm really not sure what makes you think that this should be modelled as a clock? > > > The big question is right now how to proceed with the A83T and A31s p= atches. > > > I see there three options, which one do you prefer?: > > >=20 > > > 1. Provide now placeholder patches and send new patches, if everythin= g is > > > clear and other things are mainlined > > > 2. Provide now patches as complete as possible and provide later patc= hes to > > > complete them when the R_PRCM things are mainlined > > > 3. Leave them out, till the related work is mainlined and the binding= s are > > > final. > >=20 > > Like I said, the DT *has* to be backward-compatible, so for any DT patc= h that > > you are asking to be merged, you should be prepared to support it indef= initely > > and be able to run from it, and you won't be able to change the binding= s later > > on. >=20 > I agree on your points. But is this also suitable to drivers that are > currently off tree and might be merged in one or two years? This is what we done for the Mali. The devicetree binding was first done fo= r the out-of-tree driver, and then lima/panfrost reused it. The key thing here is to have enough confidence about how the hardware work= s so that you can accurately describe it. Maxime --bsmwn6lsujflbhcr Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXp7XOQAKCRDj7w1vZxhR xY2FAP98NEADiujPOYdZcBw58gJhiTHRG5M+7cY4QmY6LLWi6wEAmaVzzE9csrhP gszgPuCUwSKxGaUpbu0VHqeb3LVqwQs= =LITU -----END PGP SIGNATURE----- --bsmwn6lsujflbhcr--