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[23.128.96.18]) by mx.google.com with ESMTP id mj2si1750298ejb.279.2020.04.21.09.18.09; Tue, 21 Apr 2020 09:18:35 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=yFSJrCHX; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729232AbgDUQQU (ORCPT + 99 others); Tue, 21 Apr 2020 12:16:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36902 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726063AbgDUQQP (ORCPT ); Tue, 21 Apr 2020 12:16:15 -0400 Received: from mail-wr1-x441.google.com (mail-wr1-x441.google.com [IPv6:2a00:1450:4864:20::441]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 05EF4C061A10 for ; Tue, 21 Apr 2020 09:16:14 -0700 (PDT) Received: by mail-wr1-x441.google.com with SMTP id t14so17055712wrw.12 for ; Tue, 21 Apr 2020 09:16:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2W/tk3xtyOOYW8CHtOYgazclqfCaFCGaEqtWfgUm9eE=; b=yFSJrCHXzK+0ituJhdbLzwgafBMyuUjGBzgA0JMzzCA25Cep4oJx6Yai4fmKmStql8 Cr/vRGokdzgkCaMKeNK6PsdnuHLNxFEgqqMYLHt6QvWzxJk4hA/eGMqWq0MR52r/YdYd OPwaum+XuII4+Qv1qtgVTE+A3RXyJ3x7gkUO4Qb/X607TXQWE1a5yYs7T1vguw0nLiPx vOn4+ck3HQwmXJJn7hL8Eu/0mCfN1ByCqQnzEFa/lMFMqbjHkt6kZ9e1AJ3ohcNDq5M6 mW6Bt9yGXekch+itGETO1iIZ2jX8Ew8Td91QUXQ5Hn8F3uzMZhrBnRDmIHDCU+Gi4aLd B+Mw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2W/tk3xtyOOYW8CHtOYgazclqfCaFCGaEqtWfgUm9eE=; b=HoLNn8IwK3He0qA/e/snknYqAbn3rjBEk8QlHLEFO2HxyEQIVZzfZlsD2EZiFiOBo4 QXLU3ky+/s8dvzBeJ/k5lNkZU8o/T4Qc9RT4tYXIvVrj6WeKqAOO3hwFzIYDCG/5I26s OVTicYQGOiKgOOWyT7SxBAW0M7a79hiwD6B/bYTJ8DlwZyWumXDwF5xFW+0fWs7XxKBw 9y9/RAqe7SGIlGoKXrljVa/gosnISOKXxk4daLjgvgPK8MUY0jkY5KvFdKTyPzrPU7Aa T22h7ZdqWFRn+sU62uQx/ESRjki2cckGoA9fHnsTIoLtRV2E8IA9axbZoUWNhMaXx3m5 tJlg== X-Gm-Message-State: AGi0PubbpoIF9xDOSJqJdhAUx61jSuxBdSP8hbDdGtPWbnZCVnyNtfs3 PVW3gURmA+Na26nlSnmgdBR4HA== X-Received: by 2002:adf:dbc2:: with SMTP id e2mr25101308wrj.264.1587485772584; Tue, 21 Apr 2020 09:16:12 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:2ec0:82b0:39cc:a07:8b48:cc56]) by smtp.gmail.com with ESMTPSA id m8sm4410873wrx.54.2020.04.21.09.16.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Apr 2020 09:16:11 -0700 (PDT) From: Neil Armstrong To: daniel@ffwll.ch, dri-devel@lists.freedesktop.org Cc: Neil Armstrong , linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Kevin Hilman Subject: [PATCH v6 5/6] drm/meson: overlay: setup overlay for Amlogic FBC Scatter Memory layout Date: Tue, 21 Apr 2020 18:15:58 +0200 Message-Id: <20200421161559.2347-6-narmstrong@baylibre.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200421161559.2347-1-narmstrong@baylibre.com> References: <20200421161559.2347-1-narmstrong@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Setup the Amlogic FBC decoder for the VD1 video overlay plane to use read the FBC header as Scatter Memory layout reference. Tested-by: Kevin Hilman Signed-off-by: Neil Armstrong --- drivers/gpu/drm/meson/meson_overlay.c | 53 ++++++++++++++++++--------- 1 file changed, 35 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/meson/meson_overlay.c b/drivers/gpu/drm/meson/meson_overlay.c index b5c502876428..6aef28767fc1 100644 --- a/drivers/gpu/drm/meson/meson_overlay.c +++ b/drivers/gpu/drm/meson/meson_overlay.c @@ -491,6 +491,10 @@ static void meson_overlay_atomic_update(struct drm_plane *plane, AMLOGIC_FBC_OPTION_MEM_SAVING)) priv->viu.vd1_afbc_mode |= AFBC_BLK_MEM_MODE; + if ((fb->modifier & __fourcc_mod_amlogic_layout_mask) == + AMLOGIC_FBC_LAYOUT_SCATTER) + priv->viu.vd1_afbc_mode |= AFBC_SCATTER_MODE; + priv->viu.vd1_afbc_en = 0x1600 | AFBC_DEC_ENABLE; priv->viu.vd1_afbc_conv_ctrl = AFBC_CONV_LBUF_LEN(256); @@ -676,23 +680,32 @@ static void meson_overlay_atomic_update(struct drm_plane *plane, } if (priv->viu.vd1_afbc) { - /* Default mode is 4k per superblock */ - unsigned long block_size = 4096; - unsigned long body_size; - - /* 8bit mem saving mode is 3072bytes per superblock */ - if (priv->viu.vd1_afbc_mode & AFBC_BLK_MEM_MODE) - block_size = 3072; - - body_size = (ALIGN(priv->viu.vd1_stride0, 64) / 64) * - (ALIGN(priv->viu.vd1_height0, 32) / 32) * - block_size; - - priv->viu.vd1_afbc_body_addr = priv->viu.vd1_addr0 >> 4; - - /* Header is after body content */ - priv->viu.vd1_afbc_head_addr = (priv->viu.vd1_addr0 + - body_size) >> 4; + if (priv->viu.vd1_afbc_mode & AFBC_SCATTER_MODE) { + /* + * In Scatter mode, the header contains the physical + * body content layout, thus the body content + * size isn't needed. + */ + priv->viu.vd1_afbc_head_addr = priv->viu.vd1_addr0 >> 4; + priv->viu.vd1_afbc_body_addr = 0; + } else { + /* Default mode is 4k per superblock */ + unsigned long block_size = 4096; + unsigned long body_size; + + /* 8bit mem saving mode is 3072bytes per superblock */ + if (priv->viu.vd1_afbc_mode & AFBC_BLK_MEM_MODE) + block_size = 3072; + + body_size = (ALIGN(priv->viu.vd1_stride0, 64) / 64) * + (ALIGN(priv->viu.vd1_height0, 32) / 32) * + block_size; + + priv->viu.vd1_afbc_body_addr = priv->viu.vd1_addr0 >> 4; + /* Header is after body content */ + priv->viu.vd1_afbc_head_addr = (priv->viu.vd1_addr0 + + body_size) >> 4; + } } priv->viu.vd1_enabled = true; @@ -755,7 +768,8 @@ static bool meson_overlay_format_mod_supported(struct drm_plane *plane, return false; } - if (layout != AMLOGIC_FBC_LAYOUT_BASIC) { + if (layout != AMLOGIC_FBC_LAYOUT_BASIC && + layout != AMLOGIC_FBC_LAYOUT_SCATTER) { DRM_DEBUG_KMS("%llx invalid layout %x\n", modifier, layout); return false; @@ -801,8 +815,11 @@ static const uint32_t supported_drm_formats[] = { }; static const uint64_t format_modifiers[] = { + DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_SCATTER, + AMLOGIC_FBC_OPTION_MEM_SAVING), DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_BASIC, AMLOGIC_FBC_OPTION_MEM_SAVING), + DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_SCATTER, 0), DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_BASIC, 0), DRM_FORMAT_MOD_LINEAR, DRM_FORMAT_MOD_INVALID, -- 2.22.0