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Date:   Wed, 22 Apr 2020 08:58:59 +0200
From:   Maxime Ripard <maxime@cerno.tech>
To:     "H. Nikolaus Schaller" <hns@goldelico.com>
Cc:     Tony Lindgren <tony@atomide.com>,
        Philipp Rossak <embed3d@gmail.com>,
        Jonathan Bakker <xc-racer2@live.ca>,
        David Airlie <airlied@linux.ie>,
        Daniel Vetter <daniel@ffwll.ch>,
        Rob Herring <robh+dt@kernel.org>,
        Mark Rutland <mark.rutland@arm.com>,
        =?utf-8?Q?Beno=C3=AEt?= Cousson <bcousson@baylibre.com>,
        Paul Cercueil <paul@crapouillou.net>,
        Ralf Baechle <ralf@linux-mips.org>,
        Paul Burton <paulburton@kernel.org>,
        James Hogan <jhogan@kernel.org>, Kukjin Kim <kgene@kernel.org>,
        Krzysztof Kozlowski <krzk@kernel.org>,
        Chen-Yu Tsai <wens@csie.org>,
        Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
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Subject: Re: [PATCH v6 00/12] ARM/MIPS: DTS: add child nodes describing the
 PVRSGX GPU present in some OMAP SoC and JZ4780 (and many more)
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On Tue, Apr 21, 2020 at 07:29:32PM +0200, H. Nikolaus Schaller wrote:
>=20
> > Am 21.04.2020 um 16:15 schrieb Tony Lindgren <tony@atomide.com>:
> >=20
> > * Maxime Ripard <maxime@cerno.tech> [200421 11:22]:
> >> On Tue, Apr 21, 2020 at 11:57:33AM +0200, Philipp Rossak wrote:
> >>> I had a look on genpd and I'm not really sure if that fits.
> >>>=20
> >>> It is basically some bit that verify that the clocks should be enable=
d or
> >>> disabled.
> >>=20
> >> No, it can do much more than that. It's a framework to control the SoC=
s power
> >> domains, so clocks might be a part of it, but most of the time it's go=
ing to be
> >> about powering up a particular device.
> >=20
> > Note that on omaps there are actually SoC module specific registers.
>=20
> Ah, I see. This is of course a difference that the TI glue logic has
> its own registers in the same address range as the sgx and this can't
> be easily handled by a common sgx driver.
>=20
> This indeed seems to be unique with omap.
>=20
> > And there can be multiple devices within a single target module on
> > omaps. So the extra dts node and device is justified there.
> >=20
> > For other SoCs, the SGX clocks are probably best handled directly
> > in pvr-drv.c PM runtime functions unless a custom hardware wrapper
> > with SoC specific registers exists.
>=20
> That is why we need to evaluate what the better strategy is.
>=20
> So we have
> a) omap which has a custom wrapper around the sgx
> b) others without, i.e. an empty (or pass-through) wrapper
>=20
> Which one do we make the "standard" and which one the "exception"?
> What are good reasons for either one?
>=20
>=20
> I am currently in strong favour of a) being standard because it
> makes the pvr-drv.c simpler and really generic (independent of
> wrapping into any SoC).
>=20
> This will likely avoid problems if we find more SoC with yet another
> scheme how the SGX clocks are wrapped.
>=20
> It also allows to handle different number of clocks (A31 seems to
> need 4, Samsung, A83 and JZ4780 one) without changing the sgx bindings
> or making big lists of conditionals. This variance would be handled
> outside the sgx core bindings and driver.

I disagree. Every other GPU binding and driver is handling that just fine, =
and
the SGX is not special in any case here.

Maxime

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Content-Type: application/pgp-signature; name="signature.asc"

-----BEGIN PGP SIGNATURE-----

iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXp/rLwAKCRDj7w1vZxhR
xcRVAP9+eh7XB+uk8H5QIqpRYRnQPao/m3tRHXHCz92z/5kY+QEA3HL1hmXIYsGR
wTCOHiq6ZSI4eoHYRySSWAqNuTf5LwI=
=1ETM
-----END PGP SIGNATURE-----

--2amunzakhfscp3kq--