Received: by 2002:a25:1985:0:0:0:0:0 with SMTP id 127csp730092ybz; Wed, 22 Apr 2020 07:01:33 -0700 (PDT) X-Google-Smtp-Source: APiQypIDPn5vw4UiaIUtzTCwfsLCZtaV9NJ4TFgdel1GbtRxfhb6BWzExG4OCmqGFpWiaP9F5XQb X-Received: by 2002:a05:6402:1bc8:: with SMTP id ch8mr22970272edb.53.1587564093398; Wed, 22 Apr 2020 07:01:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1587564093; cv=none; d=google.com; s=arc-20160816; b=Xs2ySHlMh8AMbGNcrzCgqHH8Dc1zpEYZ/K82bRoH4kHQnK3LRo3gi/KD5pk8NCzrGN QJbtE6L494vupWdMoK6lWmGmHzwTLHdOMCtig6MHa6TPHTzClsYnVU+9IWbwOLNWyBVY fgq7TVgjUfqtM1xu+NNQ2Rj+Af0ViBG9GffUlreHM+o7Dx6uLQpLEB/EMXDkM/i+L4iI +tZxgIDcW+XxaKOJFv1arWLAPf0/TP7zLaa9yecoyluZJ/TD/Z7mqfh5kLwYuJx1dWpn uvb8ZmdCArwaG8vke1cn7Sr5Xn6A8wUKsHvIEezqHbPE+dyxiNvyIo/btCW/Ch6QLn6H C2Dg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:user-agent:in-reply-to :content-disposition:mime-version:references:message-id:subject:cc :to:from:date; bh=8JShCooolgI37XElpH6OJRY4THp/S0zVXs/S8Y7Pbuk=; b=AsaQ4GU2J/3Z6XBllIWsNciJhy8fDQ4MXi51+soqsFj/i0NIPGJiCQjHpldy9I6VQS qbLjy65mwaSy1Tx/MHKRYPOKdYeRMXuG8I7I3AN4Jvh6NQlw4kQHwSg9nHXC7vbq7I75 lW3EoIeVhJZSV1JXE9Xy575s5q4L0aaLEpLDggSsXh0/dfJ6ptJR77ovAjcn+mRmtaQO kNsLy4D/xkYSYr61AvfJ+9KU5SwW1XTbyvOUEDyiqIfhVL51wHQX9P7j10ihdNqTBHUL lsvsNrOAQVeK+TC7zWp2JmxbMFZOXxHc15D5WbTXE2v0Zu/i4K4fugGxP+2PsRFi60QR Om4Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id g6si3167980edv.316.2020.04.22.07.00.58; Wed, 22 Apr 2020 07:01:33 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726912AbgDVN4r (ORCPT + 99 others); Wed, 22 Apr 2020 09:56:47 -0400 Received: from foss.arm.com ([217.140.110.172]:50342 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726389AbgDVN4r (ORCPT ); Wed, 22 Apr 2020 09:56:47 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0CBFC30E; Wed, 22 Apr 2020 06:56:47 -0700 (PDT) Received: from gaia (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6426A3F68F; Wed, 22 Apr 2020 06:56:45 -0700 (PDT) Date: Wed, 22 Apr 2020 14:56:43 +0100 From: Catalin Marinas To: Russell King - ARM Linux admin Cc: James Morse , Jonathan Cameron , info@metux.net, linux-kernel@vger.kernel.org, linuxarm@huawei.com, allison@lohutok.net, gregkh@linuxfoundation.org, Tian Tao , tglx@linutronix.de, Will Deacon , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH] arm32: fix flushcache syscall with device address Message-ID: <20200422135642.GD3585@gaia> References: <1587456514-61156-1-git-send-email-tiantao6@hisilicon.com> <20200421081239.GA15439@willie-the-truck> <20200421121651.000009f0@Huawei.com> <20200421165515.GF25745@shell.armlinux.org.uk> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200421165515.GF25745@shell.armlinux.org.uk> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Apr 21, 2020 at 05:55:16PM +0100, Russell King wrote: > On Tue, Apr 21, 2020 at 05:50:22PM +0100, James Morse wrote: > > (Subject Nit: arm64, as that is what your patch modifies) > > That is irrelevent. This is a compatibility interface which is supposed > to reflect the arm32 implementation. Augmenting a compatibility > interface to do more than what it's counterpart that it's supposed to > be compatible with is senseless. > > The API concerned is an ARM32 API which is expected to only be used > for ensuring I/D cache coherency, it is not for DMA. > > Augmenting it on ARM64 for DMA is senseless. I fully agree. I don't see any valid reason why this needs to be fixed. It looks like some broken user process trying to do cache maintenance to PoU on the mapped PCIe BAR (either inadvertently or for the wrong reasons). -- Catalin