Received: by 2002:a25:1985:0:0:0:0:0 with SMTP id 127csp1781128ybz; Thu, 23 Apr 2020 05:52:42 -0700 (PDT) X-Google-Smtp-Source: APiQypIlvVE1/u+hx1EgoMoIhM1fNiCxF48giAS7JuE3Qbbai3y/LE5ehvkQCgTkN77kzPzIXSzB X-Received: by 2002:a50:bb25:: with SMTP id y34mr2409558ede.237.1587646361919; Thu, 23 Apr 2020 05:52:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1587646361; cv=none; d=google.com; s=arc-20160816; b=znEHBhrjFIkoKQeFYQzJQ+u9bj3tIcxmuq0ImqnKpkg66dE7mIHD/FQT5SA6uRxjPV AP8JJAoYNl8FN4CJmMGyb8q5zXeBGxpK0N2T1A2mNg5ejcRN2uMrNtR8edGchqx87BwU eSWPT4QUEwiILneohl2l98W3AvQHjxiyO0F44foGuQRSfybITMKa0qwsOwGafH1pf/ET gX3qc1Rlri6wyiQG85rClCQLx5OM8ayJ0JI7BENoFPFAJB8mqGrxDAkVGUJh2pPxBLw7 D7C0PtfpE0C1vJQx5EP6eK/jJEPTplzBaw2083+piMOBRphQFvSZmfJhCsG+FwLnByRX zYXg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:in-reply-to:content-transfer-encoding :content-disposition:mime-version:references:message-id:subject:cc :to:from:date; bh=Sg543hYaUA89AN3URp0jlLcsdDn+5kJ4E9EvYRrURsc=; b=z+pCT+UCpG/L5plHWXsgbHshkpKaoTJ+g4KLAtkRD1QbM1aeGYFW28SAsc1Y/CJUH0 FOFiPgikZe068vwvIlDcAxqu3778JWmXJjJX+LV35KAtpKbbV2TPSQ7m1CmHWEHkdy0z 9aDnyAJoCBC+2pXloFm4H/UbLdg/8Ldi4O8MNqEXXWfdo/RlBbJ5zfuN8rMpa6R8/nRt WZZukLIKXSUKlUlonj7UrJHMSx+K0ZJr8Ib40DvMYUOIebAvaLiaFhdSRDLwVGqupN/K KdC/gDEtXYeH0x/KKPVdOlHC7dEzBShldkVKnbF/4T29R6ac0rE3GsHYQNdeOg1bF+dt Qk1A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id g3si1034289edp.190.2020.04.23.05.52.17; Thu, 23 Apr 2020 05:52:41 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728374AbgDWMuJ (ORCPT + 99 others); Thu, 23 Apr 2020 08:50:09 -0400 Received: from foss.arm.com ([217.140.110.172]:39262 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726444AbgDWMuJ (ORCPT ); Thu, 23 Apr 2020 08:50:09 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D73AD31B; Thu, 23 Apr 2020 05:50:08 -0700 (PDT) Received: from e110455-lin.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B7E223F6CF; Thu, 23 Apr 2020 05:50:08 -0700 (PDT) Received: by e110455-lin.cambridge.arm.com (Postfix, from userid 1000) id 767A4682F3D; Thu, 23 Apr 2020 13:50:07 +0100 (BST) Date: Thu, 23 Apr 2020 13:50:07 +0100 From: Liviu Dudau To: Bernard Zhao Cc: Brian Starkey , David Airlie , Daniel Vetter , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, opensource.kernel@vivo.com Subject: Re: [PATCH] drm/arm: cleanup coding style in arm a bit Message-ID: <20200423125007.GG364558@e110455-lin.cambridge.arm.com> References: <20200422021046.4375-1-bernard@vivo.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20200422021046.4375-1-bernard@vivo.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Bernard, On Tue, Apr 21, 2020 at 07:10:46PM -0700, Bernard Zhao wrote: > For the code logic, an alarm is thrown after failure, but the > code continues to run and returns successfully, so to the caller > the if check and return branch will never run. > The change is to make the code a bit more readable. > > Signed-off-by: Bernard Zhao > --- > drivers/gpu/drm/arm/hdlcd_crtc.c | 4 +--- > 1 file changed, 1 insertion(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/arm/hdlcd_crtc.c b/drivers/gpu/drm/arm/hdlcd_crtc.c > index af67fefed38d..32bda13250f5 100644 > --- a/drivers/gpu/drm/arm/hdlcd_crtc.c > +++ b/drivers/gpu/drm/arm/hdlcd_crtc.c > @@ -160,9 +160,7 @@ static void hdlcd_crtc_mode_set_nofb(struct drm_crtc *crtc) > hdlcd_write(hdlcd, HDLCD_REG_H_SYNC, vm.hsync_len - 1); > hdlcd_write(hdlcd, HDLCD_REG_POLARITIES, polarities); > > - err = hdlcd_set_pxl_fmt(crtc); > - if (err) > - return; > + hdlcd_set_pxl_fmt(crtc); I think you found a real bug. hdlcd_set_pxl_fmt() is not supposed to return zero if the format is not supported and here we would stop enabling the pixel clock. Do you care to send a patch for fixing the bug, rather than this one? Best regards, Liviu > > clk_set_rate(hdlcd->clk, m->crtc_clock * 1000); > } > -- > 2.26.2 > -- ==================== | I would like to | | fix the world, | | but they're not | | giving me the | \ source code! / --------------- ¯\_(ツ)_/¯