Received: by 2002:a25:1985:0:0:0:0:0 with SMTP id 127csp326558ybz; Fri, 24 Apr 2020 00:49:30 -0700 (PDT) X-Google-Smtp-Source: APiQypLOl0S/MGpndKOAsJlx+BlF7Y2iCxx9nYGSfK6hWS2RXnar2/tHS8NDTd2O0lLO6LwHYoEW X-Received: by 2002:aa7:c453:: with SMTP id n19mr6014358edr.218.1587714570434; Fri, 24 Apr 2020 00:49:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1587714570; cv=none; d=google.com; s=arc-20160816; b=x7fcLxhH1CheJ2v/U5ECoMmp/XuyXQT6O8tyR76fvEX9wa6mtYpOotg9imzbcWHyRd fjmrEXGOk5ixe2ehOjETC3okthD89MpwdOBfEEs2aHGzUZHaN2oUtoPqzcAtpcMk90yN vw9jTxITxl4d7ybR/OGVvwrRvzeATZMIgYDJiPDUQ9/iWa72NEewhaimdnEhO+osqBHf A22B134DjZGhvDKc7IlrFsaFluT7SwjNkyBrSTomg6vaQWPY5QV95LCQcAymPYdKQgRr OPvLUFrnVRqZPlPZXVaNhYrDwIJXIS73qgEc50avDmOvKKLcJqNe1tx4xMfMFSPLJB2R +jtg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:in-reply-to:content-transfer-encoding :content-disposition:mime-version:references:message-id:subject:cc :to:from:date:dkim-signature; bh=SG53LOGVaYSrSbMxtiTrlXAzhLKqp75bh+EmCNg5dN0=; b=iR6lpHCt7gHonfexe7tYMAXsT/q/XiNc28QxM4XySos+MQpaxzjcoQ7sFPnWeRhuq5 b3jecFxjZOryr92mlo03GU2k4YgvJd8lIVxty94lzNle+fPCsGmImSHC/6Cr7RTTRjx8 UL0SkcFQNVzX2CKy1ftszSoxYYg4NIdYb/XgdKEhFg+XWtZiYmE58zUH9AKeOMWXA91E WaptqESl26CzXJAW8+3U5Z6aOmmf+Y99LGxkQodCs1Hx/5Zh6RbBVU9kdx6Z3EXUnVvR BF17NxAnNVmaAKVoABxt9Taax2TPCQ9EK3/qx/kzO4sVP1Pugou/eLKBkLd3BPgOlkPF fGgQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=a+DsWnfI; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id c13si2779361edq.97.2020.04.24.00.49.07; Fri, 24 Apr 2020 00:49:30 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=a+DsWnfI; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726576AbgDXHpX (ORCPT + 99 others); Fri, 24 Apr 2020 03:45:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35886 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726028AbgDXHpX (ORCPT ); Fri, 24 Apr 2020 03:45:23 -0400 Received: from mail-wr1-x441.google.com (mail-wr1-x441.google.com [IPv6:2a00:1450:4864:20::441]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 87D97C09B045 for ; Fri, 24 Apr 2020 00:45:21 -0700 (PDT) Received: by mail-wr1-x441.google.com with SMTP id i10so9540128wrv.10 for ; Fri, 24 Apr 2020 00:45:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:content-transfer-encoding:in-reply-to; bh=SG53LOGVaYSrSbMxtiTrlXAzhLKqp75bh+EmCNg5dN0=; b=a+DsWnfI8BxEYpw24cMf1ubciUzpfQylo8DC8e2EEMjIGJAT5XO0tgJRc4zm/7UKFj yP+UatvpM1GtMmXPpD5t6YQ4MasDgMtoYBWExtSpG/3qslXrxpKJuKOxPK6aDwnRbbNW 6yJkklIByWlX/orJ1QKHiLb1RV9hXPUxXRysqlf+BZvjvB7SyZ++FH1taB7SxqUTSMKd Mj7oXh41AlY1haAGy3/VSB+UViganSyx20+MVCqJlMMbYhZ1eBZnDu7arB/dsxjdJR9g cMWMghusSfqfUS/ZTQ+cVhwDE8raguIokO5x2X3TnwoyGJPxoQ5N3TuXUvUMUuXGQXsL 2u6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to; bh=SG53LOGVaYSrSbMxtiTrlXAzhLKqp75bh+EmCNg5dN0=; b=GrJOZrrzqgCbGsfznoZoJvJG/6P2KUCCaZr0YMiA8jr24PmlIiiVTwejX3mZcnHuZd KBlwlwJRjB5PwFVtDs+L8FakyaKYoLzJ+KDuYkSn+UnWnnzwfZHM2jTeF5GksjLmjZRJ osZVsdMiE2POFAQR5X0L0ZR3YmUNc3DcnyeG93QXcNJYGlROJ4aFqwbLGUqCjAriLwG4 LwQobdRxH3EH3MT74DQEX5UxtGemuebskW4g0+TQtj8MeOtLDkjAnaFUZvH+CXxYJu3F /B5Ezcokl7afS6bAGXPsSycfKL5/XReC7p7iFBKNoLh78jrxCTlGKGxrgtociiRXuEX6 s4VQ== X-Gm-Message-State: AGi0PuaQxWZvkntmfoaaZnRnDmkmyfVMFmevjovJHRgMF4o4nNX2Mfcc SRTeq9OSbP1VmbzklfLPXWTcvhhYF9c= X-Received: by 2002:adf:82f5:: with SMTP id 108mr9200402wrc.43.1587714320260; Fri, 24 Apr 2020 00:45:20 -0700 (PDT) Received: from dell ([2.31.163.63]) by smtp.gmail.com with ESMTPSA id o3sm7034174wru.68.2020.04.24.00.45.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Apr 2020 00:45:18 -0700 (PDT) Date: Fri, 24 Apr 2020 08:45:17 +0100 From: Lee Jones To: Christophe Kerello Cc: miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, robh+dt@kernel.org, mark.rutland@arm.com, tony@atomide.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, devicetree@vger.kernel.org, marex@denx.de Subject: Re: [PATCH v2 02/12] mfd: stm32-fmc2: add STM32 FMC2 controller driver Message-ID: <20200424074517.GN3612@dell> References: <1586966256-29548-1-git-send-email-christophe.kerello@st.com> <1586966256-29548-3-git-send-email-christophe.kerello@st.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1586966256-29548-3-git-send-email-christophe.kerello@st.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 15 Apr 2020, Christophe Kerello wrote: > The driver adds the support for the STMicroelectronics FMC2 controller > found on STM32MP SOCs. > > The FMC2 functional block makes the interface with: synchronous and > asynchronous static memories (such as PSNOR, PSRAM or other > memory-mapped peripherals) and NAND flash memories. > > Signed-off-by: Christophe Kerello > --- > Changes in v2: > - remove ops from stm32_fmc2 structure > - add 2 APIs to manage FMC2 enable/disable > - add 2 APIs to manage FMC2 NWAIT shared signal > > drivers/mfd/Kconfig | 12 +++ > drivers/mfd/Makefile | 1 + > drivers/mfd/stm32-fmc2.c | 136 +++++++++++++++++++++++++ > include/linux/mfd/stm32-fmc2.h | 225 +++++++++++++++++++++++++++++++++++++++++ > 4 files changed, 374 insertions(+) > create mode 100644 drivers/mfd/stm32-fmc2.c > create mode 100644 include/linux/mfd/stm32-fmc2.h > > diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig > index 2b20329..5260582 100644 > --- a/drivers/mfd/Kconfig > +++ b/drivers/mfd/Kconfig > @@ -1922,6 +1922,18 @@ config MFD_ROHM_BD71828 > Also included is a Coulomb counter, a real-time clock (RTC), and > a 32.768 kHz clock gate. > > +config MFD_STM32_FMC2 > + tristate "Support for FMC2 controllers on STM32MP SoCs" > + depends on MACH_STM32MP157 || COMPILE_TEST > + select MFD_CORE > + select REGMAP > + select REGMAP_MMIO > + help > + Select this option to enable STM32 FMC2 driver used for FMC2 External > + Bus Interface controller and FMC2 NAND flash controller. This driver > + provides core support for the STM32 FMC2 controllers, in order to use > + the actual functionality of the device other drivers must be enabled. Not sure how many times I have to say this before people stop attempting to pass these kinds of relationships off as MFDs: A memory device and its bus is not an MFD. In a similar vain to the thousands of USB, I2C, SPI, PCI and the like devices that aren't MFDs either. Please find another way to associate your device with its bus. -- Lee Jones [李琼斯] Linaro Services Technical Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog