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From:   Leonard Crestez <leonard.crestez@nxp.com>
To:     Peng Fan <peng.fan@nxp.com>,
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Subject: Re: [PATCH V2 00/10] clk: imx: fixes and improve for i.MX8M
Thread-Topic: [PATCH V2 00/10] clk: imx: fixes and improve for i.MX8M
Thread-Index: AQHV+Fizr+1km/QCtUyii39f5J5PvQ==
Date:   Fri, 24 Apr 2020 19:30:16 +0000
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On 2020-04-18 4:45 PM, Peng Fan wrote:=0A=
>> Subject: [PATCH V2 00/10] clk: imx: fixes and improve for i.MX8M=0A=
> =0A=
> Ping...=0A=
> =0A=
> Thanks,=0A=
> Peng.=0A=
> =0A=
>>=0A=
>> From: Peng Fan <peng.fan@nxp.com>=0A=
>>=0A=
>> Patches based on for-next=0A=
>>=0A=
>> V2:=0A=
>>   Patch 7, drop wait after write, add one line comment for write twice=
=0A=
>>=0A=
>> V1:=0A=
>> Patch 1,2 is to fix the lockdep warning reported by Leonard Patch 3 is t=
o fix pll=0A=
>> mux bit Patch 4 is align with other i.MX8M using gate Patch 5 is to simp=
lify=0A=
>> i.MX8MP clk root using composite=0A=
>>=0A=
>> Patch 3~5 is actually https://patchwork.kernel.org/patch/11402761/=0A=
>> with a minimal change to patch 5 here.=0A=
>>=0A=
>> Patch 6 is to use composite core clk for A53 clk root Patch 7,8,9 is act=
ually to=0A=
>> fix CORE/BUS clk slice issue.=0A=
>>   This issue is triggerred after we update U-Boot to include  the A53 cl=
k fixes=0A=
>> to sources from PLL, not from A53 root clk,  because of the signoff timi=
ng is=0A=
>> 1GHz. U-Boot set the A53 root  mux to 2, sys pll2 500MHz. Kernel will se=
t=0A=
>> the A53 root mux to  4, sys pll1 800MHz, then gate off sys pll2 500MHz. =
Then=0A=
>> kernel  will gate off A53 root because clk_ignore_unsed, A53 directly so=
urces=0A=
>> PLL, so it is ok to gate off A53 root. However when gate off A53  root c=
lk,=0A=
>> system hang, because the original mux sys pll2 500MHz  gated off with=0A=
>> CLK_OPS_PARENT_ENABLE flag.=0A=
>>=0A=
>>   It is lucky that we not met issue for other core/bus clk slice  except=
 A53=0A=
>> ROOT core slice. But it is always triggerred after  U-Boot and Linux bot=
h=0A=
>> switch to use ARM PLL for A53 core, but  have different mux settings for=
 A53=0A=
>> root clk slice.=0A=
>>=0A=
>>   So the three patches is to address this issue.=0A=
>>=0A=
>> Patch 10 is make memrepair as critical.=0A=
>>=0A=
>> Peng Fan (10):=0A=
>>    arm64: dts: imx8m: assign clocks for A53=0A=
>>    clk: imx8m: drop clk_hw_set_parent for A53=0A=
>>    clk: imx: imx8mp: fix pll mux bit=0A=
>>    clk: imx8mp: Define gates for pll1/2 fixed dividers=0A=
>>    clk: imx8mp: use imx8m_clk_hw_composite_core to simplify code=0A=
>>    clk: imx8m: migrate A53 clk root to use composite core=0A=
>>    clk: imx: add mux ops for i.MX8M composite clk=0A=
>>    clk: imx: add imx8m_clk_hw_composite_bus=0A=
>>    clk: imx: use imx8m_clk_hw_composite_bus for i.MX8M bus clk slice=0A=
>>    clk: imx8mp: mark memrepair clock as critical=0A=
>>=0A=
>>   arch/arm64/boot/dts/freescale/imx8mm.dtsi |  10 +-=0A=
>> arch/arm64/boot/dts/freescale/imx8mn.dtsi |  10 +-=0A=
>> arch/arm64/boot/dts/freescale/imx8mp.dtsi |  11 ++-=0A=
>>   arch/arm64/boot/dts/freescale/imx8mq.dtsi |   9 +-=0A=
>>   drivers/clk/imx/clk-composite-8m.c        |  67 ++++++++++++-=0A=
>>   drivers/clk/imx/clk-imx8mm.c              |  27 +++---=0A=
>>   drivers/clk/imx/clk-imx8mn.c              |  25 +++--=0A=
>>   drivers/clk/imx/clk-imx8mp.c              | 150=0A=
>> +++++++++++++++---------------=0A=
>>   drivers/clk/imx/clk-imx8mq.c              |  29 +++---=0A=
>>   drivers/clk/imx/clk.h                     |   7 ++=0A=
>>   include/dt-bindings/clock/imx8mp-clock.h  |  28 +++++-=0A=
>>   11 files changed, 240 insertions(+), 133 deletions(-)=0A=
=0A=
For 1-6 and 10:=0A=
=0A=
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>=0A=