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[23.128.96.18]) by mx.google.com with ESMTP id pv24si3994922ejb.244.2020.04.24.15.07.50; Fri, 24 Apr 2020 15:08:14 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=2syVbBmo; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726073AbgDXWGC (ORCPT + 99 others); Fri, 24 Apr 2020 18:06:02 -0400 Received: from mail.kernel.org ([198.145.29.99]:43128 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725874AbgDXWGC (ORCPT ); Fri, 24 Apr 2020 18:06:02 -0400 Received: from mail-qt1-f178.google.com (mail-qt1-f178.google.com [209.85.160.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id A2A392098B; Fri, 24 Apr 2020 22:06:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1587765961; bh=JivJTIRgDiUIQy8eirUs45TtyuILvCgZqRvnH5Wfcmk=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=2syVbBmoK8XrkPtUfJDqtPoO+QllnBQNWmGqXWVUUPjXUdNygPj3yDGu1IkZB/ltc RY4Eubr6n1HDACvMv60r+ICK/pBsG5rUEu4y9TmhfkD9POKfJZTfhhMsmgypj2StyW EDp7nlwKG4kh9mFheZAtzuxFuQZcuePnmfbko3QE= Received: by mail-qt1-f178.google.com with SMTP id w29so9299035qtv.3; Fri, 24 Apr 2020 15:06:01 -0700 (PDT) X-Gm-Message-State: AGi0Pub/LiMMC0DLxOSUFijIItVNhJ6iSEKYC6WcP9brRlk/QSDzrlHT Pg3yqo2bCIPqJxIFFBiq3l83szafduw/Ykcy2g== X-Received: by 2002:ac8:47cb:: with SMTP id d11mr10875122qtr.136.1587765960749; Fri, 24 Apr 2020 15:06:00 -0700 (PDT) MIME-Version: 1.0 References: <20200423064808.10468-1-etienne.carriere@linaro.org> <20200423064808.10468-2-etienne.carriere@linaro.org> In-Reply-To: <20200423064808.10468-2-etienne.carriere@linaro.org> From: Rob Herring Date: Fri, 24 Apr 2020 17:05:49 -0500 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [RFC PATCH 1/2] dt-bindings: arm: Add secure-clocks binding description To: Etienne Carriere Cc: "linux-kernel@vger.kernel.org" , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , devicetree@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Apr 23, 2020 at 1:49 AM Etienne Carriere wrote: > > Describe how clocks property can leverage secure- property prefix > for clocks handled exclusively or shared by secure and non-secure > worlds. > > Signed-off-by: Etienne Carriere > --- > .../devicetree/bindings/arm/secure.txt | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/secure.txt b/Documentation/devicetree/bindings/arm/secure.txt > index f27bbff2c780..9bc94921f2a6 100644 > --- a/Documentation/devicetree/bindings/arm/secure.txt > +++ b/Documentation/devicetree/bindings/arm/secure.txt > @@ -53,6 +53,25 @@ Valid Secure world properties > status = "disabled"; /* disabled in both */ > status = "disabled"; secure-status = "disabled"; /* disabled in both */ > > +- secure-clocks : specifies the Phandle list secure world shall use > + for the related clocks whereas property "clocks" specifies the > + clock Phandle list non-secure shall use for the that clocks. > + This configuration can apply for example when a hardware clock is > + shared by the 2 worlds and the hardware implements a specific interface > + for each world, i.e.: > + > + clocks = <&clk DMA_NS>; /* NS relies on clock handle DMA_NS */ > + secure-clocks = <&clk DMA_S>; /* S relies on clock handle DMA_S */ The device has to know what it's clocks are for and should know if some clocks are secure only. > + Another example where use of "clocks" and "secure-clocks" can apply > + is when hardware implements a clock that secure and non-secure must > + share, as a shared GPIO bank clock, and secure world relies on clock > + device driver whereas non-secure world relies on a software service > + exposed by secure world as SCMI clock device. I.e.: > + > + clocks = <&scmi_clk 2>; /* NS relies on SCMI resources */ > + secure-clocks= <&clk 5>; /* S accesses the SoC reset interfaces */ If you have this case, I don't think this is the solution. I don't think it scales well and you probably need separate DTs. It's something to solve in the system DT project. Rob