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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id h31sm9123564pjb.33.2020.04.26.04.07.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Apr 2020 04:07:44 -0700 (PDT) From: Zong Li To: palmer@dabbelt.com, paul.walmsley@sifive.com, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, anup@brainfault.org Cc: david.abdurachmanov@sifive.com, Zong Li Subject: [PATCH] irqchip/sifive-plic: allow many cores to handle IRQs Date: Sun, 26 Apr 2020 19:07:40 +0800 Message-Id: <20200426110740.123638-1-zong.li@sifive.com> X-Mailer: git-send-email 2.26.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Currently, driver forces the IRQs to be handled by only one core. This patch provides the way to enable others cores to handle IRQs if needed, so users could decide how many cores they wanted on default by boot argument. Use 'irqaffinity' boot argument to determine affinity. If there is no irqaffinity in dts or kernel configuration, use irq default affinity, so all harts would try to claim IRQ. For example, add irqaffinity=0 in chosen node to set irq affinity to hart 0. It also supports more than one harts to handle irq, such as set irqaffinity=0,3,4. You can change IRQ affinity from user-space using procfs. For example, you can make CPU0 and CPU2 serve IRQ together by the following command: echo 4 > /proc/irq//smp_affinity Signed-off-by: Zong Li --- drivers/irqchip/irq-sifive-plic.c | 21 +++++++-------------- 1 file changed, 7 insertions(+), 14 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index d0a71febdadc..bc1440d54185 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -111,15 +111,12 @@ static inline void plic_irq_toggle(const struct cpumask *mask, static void plic_irq_unmask(struct irq_data *d) { struct cpumask amask; - unsigned int cpu; struct plic_priv *priv = irq_get_chip_data(d->irq); cpumask_and(&amask, &priv->lmask, cpu_online_mask); - cpu = cpumask_any_and(irq_data_get_affinity_mask(d), - &amask); - if (WARN_ON_ONCE(cpu >= nr_cpu_ids)) - return; - plic_irq_toggle(cpumask_of(cpu), d, 1); + cpumask_and(&amask, &amask, irq_data_get_affinity_mask(d)); + + plic_irq_toggle(&amask, d, 1); } static void plic_irq_mask(struct irq_data *d) @@ -133,24 +130,20 @@ static void plic_irq_mask(struct irq_data *d) static int plic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, bool force) { - unsigned int cpu; struct cpumask amask; struct plic_priv *priv = irq_get_chip_data(d->irq); cpumask_and(&amask, &priv->lmask, mask_val); if (force) - cpu = cpumask_first(&amask); + cpumask_copy(&amask, mask_val); else - cpu = cpumask_any_and(&amask, cpu_online_mask); - - if (cpu >= nr_cpu_ids) - return -EINVAL; + cpumask_and(&amask, &amask, cpu_online_mask); plic_irq_toggle(&priv->lmask, d, 0); - plic_irq_toggle(cpumask_of(cpu), d, 1); + plic_irq_toggle(&amask, d, 1); - irq_data_update_effective_affinity(d, cpumask_of(cpu)); + irq_data_update_effective_affinity(d, &amask); return IRQ_SET_MASK_OK_DONE; } -- 2.26.1