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Subject: RE: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite clk
Thread-Topic: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite clk
Thread-Index: AQHV+FjOyMJp4JjxAkWF8jtS4KMMQqiM9zMA
Date:   Mon, 27 Apr 2020 09:15:32 +0000
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> Subject: Re: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite
> clk
>=20
> On 2020-03-12 12:27 PM, Peng Fan wrote:
> > From: Peng Fan <peng.fan@nxp.com>
> >
> > The CORE/BUS root slice has following design, simplied graph:
> > The difference is core not have pre_div block.
> > A composite core/bus clk has 8 inputs for mux to select, saying clk[0-7=
].
> >
> >              SEL_A  GA
> >              +--+  +-+
> >              |  +->+ +------+
> > CLK[0-7]--->+  |  +-+      |
> >         |    |  |      +----v---+    +----+
> >         |    +--+      |pre_diva+---->    |  +---------+
> >         |              +--------+    |mux +--+post_div |
> >         |    +--+      |pre_divb+--->+    |  +---------+
> >         |    |  |      +----^---+    +----+
> >         +--->+  |  +-+      |
> >              |  +->+ +------+
> >              +--+  +-+
> >              SEL_B  GB
> >
> > There will be system hang, when doing the following steps:
> > 1. switch mux from clk0 to clk1
> > 2. gate off clk0
> > 3. swtich from clk1 to clk2, or gate off clk1
> >
> > Step 3 triggers system hang.
> >
> > If we skip step2, keep clk0 on, step 3 will not trigger system hang.
> > However we have CLK_OPS_PARENT_ENABLE flag, which will unprepare
> > disable the clk0 which will not be used.
>=20
> As far as I understand when switching from clk1 to clk2 this is done by
> temporarily switching the rightmost SELECT mux to whatever was in the
> spare SEL, which is essentially arbitrary from linux POV.

No. The fixes in this patches has been confirmed by IC design owner

>=20
> This is quite unexpected but in theory it might be desirable to use a thi=
rd
> parent as a fallback.

No. this will make things complicated. To CCM SEL_A and SEL_B,
it is controlled by a hardware counter. Saying you write n times to
the target interface.

The mux will use n % 2 to choose SEL_A or SEL_B. write twice
to make sure SEL_A and SEL_B has the same value.

Thanks,
Peng.

>=20
> >
> > To address this issue, we could use following simplied software flow:
> > After the first target register set
> > wait the target register set finished
> > set the target register set again
> > wait the target register set finished
> >
> > The upper flow will make sure SEL_A and SEL_B both set the new mux,
> > but with only one path gate on.
> > And there will be no system hang anymore with step3.
>=20
> Your fix tries to work around this scenario by always setting the mux val=
ue in
> SEL_A and SEL_B to the same value after each set_parent operation.
>=20
> But what if SEL_A and SEL_B are different at linux boot time and the firs=
t
> reparenting is done *after* disabling unused clocks? This doesn't happen =
for
> A53 because it's reparented during clock provider probe but maybe this
> scenario could be contrived if bootloader touches one of the other bus sl=
ices.
>=20
> It might be extra safe to assign the parent of the spare mux at the start=
 of
> each set_parent call. This could even be done on probe and this way would=
n't
> have to duplicate mux_ops just to do a double write.
>=20
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > ---
> >
> > V2:
> >   Drop wait after write, add one line comment for write twice.
> >
> >   drivers/clk/imx/clk-composite-8m.c | 62
> +++++++++++++++++++++++++++++++++++++-
> >   1 file changed, 61 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/imx/clk-composite-8m.c
> > b/drivers/clk/imx/clk-composite-8m.c
> > index 99773519b5a5..eae02c151ced 100644
> > --- a/drivers/clk/imx/clk-composite-8m.c
> > +++ b/drivers/clk/imx/clk-composite-8m.c
> > @@ -24,6 +24,12 @@
> >
> >   #define PCG_CGC_SHIFT		28
> >
> > +#define PRE_REG_OFF		0x30
> > +#define PRE_MUXA_SHIFT		24
> > +#define PRE_MUXA_MASK		0x7
> > +#define PRE_MUXB_SHIFT		8
> > +#define PRE_MUXB_MASK		0x7
>=20
> These are unused.
>=20
> > +
> >   static unsigned long imx8m_clk_composite_divider_recalc_rate(struct
> clk_hw *hw,
> >   						unsigned long parent_rate)
> >   {
> > @@ -124,6 +130,57 @@ static const struct clk_ops
> imx8m_clk_composite_divider_ops =3D {
> >   	.set_rate =3D imx8m_clk_composite_divider_set_rate,
> >   };
> >
> > +static u8 imx8m_clk_composite_mux_get_parent(struct clk_hw *hw) {
> > +	struct clk_mux *mux =3D to_clk_mux(hw);
> > +	u32 val;
> > +
> > +	val =3D readl(mux->reg) >> mux->shift;
> > +	val &=3D mux->mask;
> > +
> > +	return clk_mux_val_to_index(hw, mux->table, mux->flags, val); }
> > +
> > +static int imx8m_clk_composite_mux_set_parent(struct clk_hw *hw, u8
> > +index) {
> > +	struct clk_mux *mux =3D to_clk_mux(hw);
> > +	u32 val =3D clk_mux_index_to_val(mux->table, mux->flags, index);
> > +	unsigned long flags =3D 0;
> > +	u32 reg;
> > +
> > +	if (mux->lock)
> > +		spin_lock_irqsave(mux->lock, flags);
> > +
> > +	reg =3D readl(mux->reg);
> > +	reg &=3D ~(mux->mask << mux->shift);
> > +	val =3D val << mux->shift;
> > +	reg |=3D val;
> > +	/* write twice to make sure SEL_A/B point the same mux */
> > +	writel(reg, mux->reg);
> > +	writel(reg, mux->reg);
> > +
> > +	if (mux->lock)
> > +		spin_unlock_irqrestore(mux->lock, flags);
> > +
> > +	return 0;
> > +}
> > +
> > +static int
> > +imx8m_clk_composite_mux_determine_rate(struct clk_hw *hw,
> > +				       struct clk_rate_request *req) {
> > +	struct clk_mux *mux =3D to_clk_mux(hw);
> > +
> > +	return clk_mux_determine_rate_flags(hw, req, mux->flags); }
> > +
> > +
> > +const struct clk_ops imx8m_clk_composite_mux_ops =3D {
> > +	.get_parent =3D imx8m_clk_composite_mux_get_parent,
> > +	.set_parent =3D imx8m_clk_composite_mux_set_parent,
> > +	.determine_rate =3D imx8m_clk_composite_mux_determine_rate,
> > +};
> > +
> >   struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
> >   					const char * const *parent_names,
> >   					int num_parents, void __iomem *reg, @@
> -136,6 +193,7 @@ struct
> > clk_hw *imx8m_clk_hw_composite_flags(const char *name,
> >   	struct clk_gate *gate =3D NULL;
> >   	struct clk_mux *mux =3D NULL;
> >   	const struct clk_ops *divider_ops;
> > +	const struct clk_ops *mux_ops;
> >
> >   	mux =3D kzalloc(sizeof(*mux), GFP_KERNEL);
> >   	if (!mux)
> > @@ -157,10 +215,12 @@ struct clk_hw
> *imx8m_clk_hw_composite_flags(const char *name,
> >   		div->shift =3D PCG_DIV_SHIFT;
> >   		div->width =3D PCG_CORE_DIV_WIDTH;
> >   		divider_ops =3D &clk_divider_ops;
> > +		mux_ops =3D &imx8m_clk_composite_mux_ops;
> >   	} else {
> >   		div->shift =3D PCG_PREDIV_SHIFT;
> >   		div->width =3D PCG_PREDIV_WIDTH;
> >   		divider_ops =3D &imx8m_clk_composite_divider_ops;
> > +		mux_ops =3D &clk_mux_ops;
> >   	}
> >
> >   	div->lock =3D &imx_ccm_lock;
> > @@ -176,7 +236,7 @@ struct clk_hw
> *imx8m_clk_hw_composite_flags(const char *name,
> >   	gate->lock =3D &imx_ccm_lock;
> >
> >   	hw =3D clk_hw_register_composite(NULL, name, parent_names,
> num_parents,
> > -			mux_hw, &clk_mux_ops, div_hw,
> > +			mux_hw, mux_ops, div_hw,
> >   			divider_ops, gate_hw, &clk_gate_ops, flags);
> >   	if (IS_ERR(hw))
> >   		goto fail;
> >