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Subject: Re: [PATCH 1/3] arm64: dts: ti: am654: Add DSS node
To:     Tomi Valkeinen <tomi.valkeinen@ti.com>, Nishanth Menon <nm@ti.com>,
        Rob Herring <robh+dt@kernel.org>,
        <linux-arm-kernel@lists.infradead.org>,
        <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        Jyri Sarha <jsarha@ti.com>
References: <20200422091512.950-1-tomi.valkeinen@ti.com>
From:   Tero Kristo <t-kristo@ti.com>
Message-ID: <591ddc8e-b45a-5a36-ae81-e1b92727dd2d@ti.com>
Date:   Mon, 27 Apr 2020 13:08:42 +0300
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On 22/04/2020 12:15, Tomi Valkeinen wrote:
> From: Jyri Sarha <jsarha@ti.com>
> 
> Add DSS node to k3-am65-main.dtsi with labels for board specific
> support and syscon node for oldi-io-ctrl.
> 
> Signed-off-by: Jyri Sarha <jsarha@ti.com>
> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
> ---
>   arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 44 ++++++++++++++++++++++++
>   1 file changed, 44 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> index 11887c72f23a..7d1bc991708e 100644
> --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> @@ -287,6 +287,11 @@
>   			mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */
>   					<0x4090 0x3>; /* SERDES1 lane select */
>   		};
> +
> +		dss_oldi_io_ctrl: dss_oldi_io_ctrl@41E0 {
> +			compatible = "syscon";
> +			reg = <0x0000041E0 0x14>;
> +		};
>   	};
>   
>   	dwc3_0: dwc3@4000000 {
> @@ -746,4 +751,43 @@
>   			};
>   		};
>   	};
> +
> +	dss: dss@04a00000 {
> +		compatible = "ti,am65x-dss";
> +		reg =	<0x0 0x04a00000 0x0 0x1000>, /* common */
> +			<0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
> +			<0x0 0x04a06000 0x0 0x1000>, /* vid */
> +			<0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
> +			<0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
> +			<0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
> +			<0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
> +		reg-names = "common", "vidl1", "vid",
> +			"ovr1", "ovr2", "vp1", "vp2";
> +
> +		ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
> +
> +		power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
> +
> +		clocks =	<&k3_clks 67 1>,
> +				<&k3_clks 216 1>,
> +				<&k3_clks 67 2>;
> +		clock-names = "fck", "vp1", "vp2";
> +
> +		/*
> +		 * Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via
> +		 * DIV1. See "Figure 12-3365. DSS Integration"
> +		 * in AM65x TRM for details.
> +		 */
> +		assigned-clocks = <&k3_clks 67 2>;
> +		assigned-clock-parents = <&k3_clks 67 5>;
> +
> +		interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
> +
> +		status = "disabled";

Any reason why the node is disabled? Are you planning to enable it 
somewhere later on, or is that left for the user to do?

-Tero

> +
> +		dss_ports: ports {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +	};
>   };
> 

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