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From:   Geert Uytterhoeven <geert@linux-m68k.org>
Date:   Mon, 27 Apr 2020 12:18:50 +0200
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Subject: Re: [PATCH 08/10] clk: renesas: cpg-mssr: Add R8A7742 support
To:     "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Cc:     Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        Magnus Damm <magnus.damm@gmail.com>,
        Russell King <linux@armlinux.org.uk>,
        Marian-Cristian Rotariu 
        <marian-cristian.rotariu.rb@bp.renesas.com>,
        linux-clk <linux-clk@vger.kernel.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@vger.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        Linux ARM <linux-arm-kernel@lists.infradead.org>,
        Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
        Linux PM list <linux-pm@vger.kernel.org>
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Hi Prabhakar,

On Mon, Apr 27, 2020 at 12:07 PM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
> On Mon, Apr 27, 2020 at 10:10 AM Geert Uytterhoeven
> <geert@linux-m68k.org> wrote:
> > On Thu, Apr 23, 2020 at 11:41 PM Lad Prabhakar
> > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > > Add RZ/G1H (R8A7742) Clock Pulse Generator / Module Standby and Software
> > > Reset support, using the CPG/MSSR driver core and the common R-Car Gen2
> > > (and RZ/G) code.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
> >
> > Thanks for your patch!
> >
> > > --- /dev/null
> > > +++ b/drivers/clk/renesas/r8a7742-cpg-mssr.c
> >
> > > +static struct cpg_core_clk r8a7742_core_clks[] __initdata = {

> > > +       DEF_FIXED("zg",    R8A7742_CLK_ZG,      CLK_PLL1,           3, 1),

> > > +static int __init r8a7742_cpg_mssr_init(struct device *dev)
> > > +{
> > > +       const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
> > > +       struct device_node *np = dev->of_node;
> > > +       unsigned int i;
> > > +       u32 cpg_mode;
> > > +       int error;
> > > +
> > > +       error = rcar_rst_read_mode_pins(&cpg_mode);
> > > +       if (error)
> > > +               return error;
> > > +
> > > +       cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
> > > +
> > > +       if (of_device_is_compatible(np, "renesas,r8a7742-cpg-mssr")) {
> > > +               /* RZ/G1H uses a 1/3 divider for ZG */
> > > +               for (i = 0; i < ARRAY_SIZE(r8a7742_core_clks); i++)
> > > +                       if (r8a7742_core_clks[i].id == R8A7742_CLK_ZG) {
> > > +                               r8a7742_core_clks[i].div = 3;
> > > +                               break;
> > > +                       }
> > > +       }
> >
> > Do you really need this part? (copied from r8a7743-cpg-mssr.c ;-)
> > If you remove it, r8a7742_core_clks[] can be const, and <linux/of.h> is
> > no longer needed,
> >
> I haven't come far enough to test the GPU yet, so Ill drop this for
> now and add this later if needed.

The divider is already set to 3 in the table above.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds