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Subject: Re: [PATCH] arm64: dts: ti: k3-am65-main: Add ehrpwm nodes
To:     Vignesh Raghavendra <vigneshr@ti.com>, Nishanth Menon <nm@ti.com>,
        Rob Herring <robh+dt@kernel.org>
CC:     <linux-arm-kernel@lists.infradead.org>,
        <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
References: <20200322112630.25541-1-vigneshr@ti.com>
From:   Tero Kristo <t-kristo@ti.com>
Message-ID: <0ebef6a3-7b0e-fc3a-3101-7e1a135093b0@ti.com>
Date:   Mon, 27 Apr 2020 13:28:09 +0300
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On 22/03/2020 13:26, Vignesh Raghavendra wrote:
> Add DT nodes for all ehrpwm instances present on AM654 EVM.
> 
> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
> ---
> 
> clk driver and bindings has been merged to clk-next tree.

Queued up for 5.8, thanks.

-Tero

> 
>   arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 60 ++++++++++++++++++++++++
>   1 file changed, 60 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> index e5df20a2d2f9..da6427bed801 100644
> --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> @@ -285,6 +285,12 @@ serdes_mux: mux-controller {
>   			mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */
>   					<0x4090 0x3>; /* SERDES1 lane select */
>   		};
> +
> +		ehrpwm_tbclk: syscon@4140 {
> +			compatible = "ti,am654-ehrpwm-tbclk", "syscon";
> +			reg = <0x4140 0x18>;
> +			#clock-cells = <1>;
> +		};
>   	};
>   
>   	dwc3_0: dwc3@4000000 {
> @@ -742,4 +748,58 @@ csi2_0: port@0 {
>   			};
>   		};
>   	};
> +
> +	ehrpwm0: pwm@3000000 {
> +		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
> +		#pwm-cells = <3>;
> +		reg = <0x0 0x3000000 0x0 0x100>;
> +		power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
> +		clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>;
> +		clock-names = "tbclk", "fck";
> +	};
> +
> +	ehrpwm1: pwm@3010000 {
> +		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
> +		#pwm-cells = <3>;
> +		reg = <0x0 0x3010000 0x0 0x100>;
> +		power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
> +		clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>;
> +		clock-names = "tbclk", "fck";
> +	};
> +
> +	ehrpwm2: pwm@3020000 {
> +		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
> +		#pwm-cells = <3>;
> +		reg = <0x0 0x3020000 0x0 0x100>;
> +		power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
> +		clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>;
> +		clock-names = "tbclk", "fck";
> +	};
> +
> +	ehrpwm3: pwm@3030000 {
> +		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
> +		#pwm-cells = <3>;
> +		reg = <0x0 0x3030000 0x0 0x100>;
> +		power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
> +		clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>;
> +		clock-names = "tbclk", "fck";
> +	};
> +
> +	ehrpwm4: pwm@3040000 {
> +		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
> +		#pwm-cells = <3>;
> +		reg = <0x0 0x3040000 0x0 0x100>;
> +		power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>;
> +		clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>;
> +		clock-names = "tbclk", "fck";
> +	};
> +
> +	ehrpwm5: pwm@3050000 {
> +		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
> +		#pwm-cells = <3>;
> +		reg = <0x0 0x3050000 0x0 0x100>;
> +		power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>;
> +		clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>;
> +		clock-names = "tbclk", "fck";
> +	};
>   };
> 

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