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Subject: Re: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite clk
Thread-Topic: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite clk
Thread-Index: AQHV+FjQMBLZK1sUBkmPtGWbyCJKZA==
Date:   Mon, 27 Apr 2020 19:34:41 +0000
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On 2020-04-27 12:15 PM, Peng Fan wrote:=0A=
>> Subject: Re: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite=
=0A=
>> clk=0A=
>>=0A=
>> On 2020-03-12 12:27 PM, Peng Fan wrote:=0A=
>>> From: Peng Fan <peng.fan@nxp.com>=0A=
>>>=0A=
>>> The CORE/BUS root slice has following design, simplied graph:=0A=
>>> The difference is core not have pre_div block.=0A=
>>> A composite core/bus clk has 8 inputs for mux to select, saying clk[0-7=
].=0A=
>>>=0A=
>>>               SEL_A  GA=0A=
>>>               +--+  +-+=0A=
>>>               |  +->+ +------+=0A=
>>> CLK[0-7]--->+  |  +-+      |=0A=
>>>          |    |  |      +----v---+    +----+=0A=
>>>          |    +--+      |pre_diva+---->    |  +---------+=0A=
>>>          |              +--------+    |mux +--+post_div |=0A=
>>>          |    +--+      |pre_divb+--->+    |  +---------+=0A=
>>>          |    |  |      +----^---+    +----+=0A=
>>>          +--->+  |  +-+      |=0A=
>>>               |  +->+ +------+=0A=
>>>               +--+  +-+=0A=
>>>               SEL_B  GB=0A=
>>>=0A=
>>> There will be system hang, when doing the following steps:=0A=
>>> 1. switch mux from clk0 to clk1=0A=
>>> 2. gate off clk0=0A=
>>> 3. swtich from clk1 to clk2, or gate off clk1=0A=
>>>=0A=
>>> Step 3 triggers system hang.=0A=
>>>=0A=
>>> If we skip step2, keep clk0 on, step 3 will not trigger system hang.=0A=
>>> However we have CLK_OPS_PARENT_ENABLE flag, which will unprepare=0A=
>>> disable the clk0 which will not be used.=0A=
>>=0A=
>> As far as I understand when switching from clk1 to clk2 this is done by=
=0A=
>> temporarily switching the rightmost SELECT mux to whatever was in the=0A=
>> spare SEL, which is essentially arbitrary from linux POV.=0A=
> =0A=
> No. The fixes in this patches has been confirmed by IC design owner=0A=
> =0A=
>>=0A=
>> This is quite unexpected but in theory it might be desirable to use a th=
ird=0A=
>> parent as a fallback.=0A=
> =0A=
> No. this will make things complicated. To CCM SEL_A and SEL_B,=0A=
> it is controlled by a hardware counter. Saying you write n times to=0A=
> the target interface.=0A=
> =0A=
> The mux will use n % 2 to choose SEL_A or SEL_B. write twice=0A=
> to make sure SEL_A and SEL_B has the same value.=0A=
=0A=
What if SEL_A and SEL_B have different values on boot? The first time =0A=
linux does set_parent it will switch to the other SEL_X which might be off.=
=0A=