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Reply-To: vadivel.muruganx.ramuthevar@linux.intel.com
Subject: Re: [PATCH v3 2/2] mtd: rawnand: Add NAND controller support on Intel
 LGM SoC
To:     Boris Brezillon <boris.brezillon@collabora.com>
Cc:     Miquel Raynal <miquel.raynal@bootlin.com>,
        linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org,
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        masonccyang@mxic.com.tw, andriy.shevchenko@intel.com
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From:   "Ramuthevar, Vadivel MuruganX" 
        <vadivel.muruganx.ramuthevar@linux.intel.com>
Message-ID: <f72b5ae0-b0ac-61b8-8f64-c0e0f48afe02@linux.intel.com>
Date:   Tue, 28 Apr 2020 14:50:35 +0800
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Hi Boris,

On 28/4/2020 2:47 pm, Boris Brezillon wrote:
> On Tue, 28 Apr 2020 14:40:58 +0800
> "Ramuthevar, Vadivel MuruganX"
> <vadivel.muruganx.ramuthevar@linux.intel.com> wrote:
> 
>> Hi Boris,
>>
>> On 28/4/2020 2:27 pm, Boris Brezillon wrote:
>>> On Tue, 28 Apr 2020 14:17:30 +0800
>>> "Ramuthevar, Vadivel MuruganX"
>>> <vadivel.muruganx.ramuthevar@linux.intel.com> wrote:
>>>    
>>>> Hi Miquel,
>>>>
>>>>       Thank you very much for the review comments and your time...
>>>>
>>>> On 27/4/2020 11:51 pm, Miquel Raynal wrote:
>>>>> Hi Ramuthevar,
>>>>>       
>>>>>>> +static int ebu_nand_probe(struct platform_device *pdev)
>>>>>>> +{
>>>>>>> +	struct device *dev = &pdev->dev;
>>>>>>> +	struct ebu_nand_controller *ebu_host;
>>>>>>> +	struct nand_chip *nand;
>>>>>>> +	phys_addr_t nandaddr_pa;
>>>>>>> +	struct mtd_info *mtd;
>>>>>>> +	struct resource *res;
>>>>>>> +	int ret;
>>>>>>> +	u32 cs;
>>>>>>> +
>>>>>>> +	ebu_host = devm_kzalloc(dev, sizeof(*ebu_host), GFP_KERNEL);
>>>>>>> +	if (!ebu_host)
>>>>>>> +		return -ENOMEM;
>>>>>>> +
>>>>>>> +	ebu_host->dev = dev;
>>>>>>> +	nand_controller_init(&ebu_host->controller);
>>>>>>> +
>>>>>>> +	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ebunand");
>>>>>>> +	ebu_host->ebu_addr = devm_ioremap_resource(&pdev->dev, res);
>>>>>>> +	if (IS_ERR(ebu_host->ebu_addr))
>>>>>>> +		return PTR_ERR(ebu_host->ebu_addr);
>>>>>>> +
>>>>>>> +	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hsnand");
>>>>>>> +	ebu_host->nand_addr = devm_ioremap_resource(&pdev->dev, res);
>>>>>>> +	if (IS_ERR(ebu_host->nand_addr))
>>>>>>> +		return PTR_ERR(ebu_host->nand_addr);
>>>>>>> +
>>>>>>> +	ret = device_property_read_u32(dev, "nand,cs", &cs);
>>>>>>
>>>>>> CS ids should be encoded in the reg property (see [1]).
>>>>>
>>>>> Is it your choice to only support a single CS or is it actually a
>>>>> controller limitation?
>>>>
>>>> Yes , its controller limitation to support only one CS
>>>
>>> I'm pretty sure that's not true, otherwise you wouldn't have to select
>>> the CS you want to use :P.
>>
>> At a time it supports only one chip select.
> 
> Yes, like 99% of the NAND controllers, but that doesn't mean you can't
> support multi-CS chips. All you have to do is attach an array of
> ebu_nand_cs to your ebu_nand_chip (as done in the atmel driver I
> pointed to). nand_operation.cs tells you which CS (index in your
> ebu_nand_cs array) a specific operation is targeting, and you can pick
> the right MMIO range/reg value based on that.

Agreed, sure I will add that and update next series of patches .

Thanks! a lot Boris

Regards
Vadivel
>